add check netlist naming conflict command and functions

openfpga/src/base/check_netlist_naming_conflict.cpp

@@ -0,0 +1,92 @@
+/********************************************************************
+ * This file includes functions to detect and correct any naming
+ * in the users' BLIF netlist that violates the syntax of OpenFPGA
+ * fabric generator, i.e., Verilog generator and SPICE generator
+ *******************************************************************/
+#include <string>
+
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "check_netlist_naming_conflict.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function aims to check if the name contains any of the 
+ * sensitive characters in the list
+ *******************************************************************/
+static 
+bool name_contain_sensitive_chars(const std::string& name, 
+                                  const std::string& sensitive_chars) {
+  for (const char& sensitive_char : sensitive_chars) {
+    /* Return true since we find a characters */
+    if (std::string::npos != name.find(sensitive_char)) {
+      return true;
+    }
+  }
+
+  return false;
+}
+
+/********************************************************************
+ * Detect and report any naming conflict by checking a list of 
+ * sensitive characters
+ * - Iterate over all the blocks and see if any block name contain 
+ *   any sensitive character
+ * - Iterate over all the nets and see if any net name contain 
+ *   any sensitive character
+ *******************************************************************/
+static 
+void detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
+                                    const std::string& sensitive_chars) {
+  size_t num_conflicts = 0;
+
+  /* Walk through blocks in the netlist */
+  for (const auto& block : atom_netlist.blocks()) {
+    const std::string& block_name = atom_netlist.block_name(block);
+    if (true == name_contain_sensitive_chars(block_name, sensitive_chars)) {
+      VTR_LOG("Block '%s' violates the syntax requirement by OpenFPGA!\n",
+              block_name.c_str());
+      num_conflicts++;
+    }
+  }
+
+  /* Walk through nets in the netlist */
+  for (const auto& net : atom_netlist.nets()) {
+    const std::string& net_name = atom_netlist.net_name(net);
+    if (true == name_contain_sensitive_chars(net_name, sensitive_chars)) {
+      VTR_LOG("Net '%s' violates the syntax requirement by OpenFPGA!\n",
+              net_name.c_str());
+      num_conflicts++;
+    }
+  }
+
+  if (0 < num_conflicts) {
+    VTR_LOG("Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
+            num_conflicts);
+  }
+} 
+
+/********************************************************************
+ * Top-level function to detect and correct any naming
+ * in the users' BLIF netlist that violates the syntax of OpenFPGA
+ * fabric generator, i.e., Verilog generator and SPICE generator
+ *******************************************************************/
+void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                   const Command& cmd, const CommandContext& cmd_context) {
+  const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/");
+
+  /* Do the main job first: detect any naming in the BLIF netlist that violates the syntax */
+  detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
+  
+} 
+
+} /* end namespace openfpga */
+

openfpga/src/base/check_netlist_naming_conflict.h

@@ -0,0 +1,23 @@
+#ifndef CHECK_NETLIST_NAMING_CONFLICT_H
+#define CHECK_NETLIST_NAMING_CONFLICT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                   const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/base/openfpga_setup_command.cpp

@@ -5,16 +5,22 @@
  *******************************************************************/
 #include "openfpga_read_arch.h"
 #include "openfpga_link_arch.h"
+#include "check_netlist_naming_conflict.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
 void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'vpr' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
+
   /* Add a new class of commands */
   ShellCommandClassId openfpga_setup_cmd_class = shell.add_command_class("OpenFPGA setup");
 
-  /* Command 'read_openfpga_arch' */
+  /******************************** 
+   * Command 'read_openfpga_arch' 
+   */
   Command shell_cmd_read_arch("read_openfpga_arch");
   /* Add an option '--file' in short '-f'*/
   CommandOptionId read_arch_opt_file = shell_cmd_read_arch.add_option("file", true, "file path to the architecture XML");
@@ -26,7 +32,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
 
-  /* Command 'write_openfpga_arch' */
+  /******************************** 
+   * Command 'write_openfpga_arch' 
+   */
   Command shell_cmd_write_arch("write_openfpga_arch");
   /* Add an option '--file' in short '-f'*/
   CommandOptionId write_arch_opt_file = shell_cmd_write_arch.add_option("file", true, "file path to the architecture XML");
@@ -40,7 +48,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
   shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
 
-  /* Command 'link_openfpga_arch' */
+  /******************************** 
+   * Command 'link_openfpga_arch' 
+   */
   Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
   
   /* Add command 'link_openfpga_arch' to the Shell */
@@ -48,12 +58,28 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
   /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
   std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
   shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_link_openfpga_arch);
 
+  /******************************************* 
+   * Command 'check_netlist_naming_conflict'
+   */ 
+  Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
+  /* Add an option '--correction' */
+  shell_cmd_check_netlist_naming_conflict.add_option("correction", false, "Apply correction to any conflicts found");
+  /* Add an option '--report' */
+  CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");
+  shell_cmd_check_netlist_naming_conflict.set_option_require_value(check_netlist_opt_rpt, openfpga::OPT_STRING);
+
+  /* Add command 'check_netlist_naming_conflict' to the Shell */
+  ShellCommandId shell_cmd_check_netlist_naming_conflict_id = shell.add_command(shell_cmd_check_netlist_naming_conflict, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
+  shell.set_command_class(shell_cmd_check_netlist_naming_conflict_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_check_netlist_naming_conflict_id, check_netlist_naming_conflict);
+  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  std::vector<ShellCommandId> cmd_dependency_check_netlist_naming_conflict(1, shell_cmd_vpr_id);
+  shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_check_netlist_naming_conflict);
 } 
 
 } /* end namespace openfpga */

openfpga/test_script/s298.openfpga

@@ -7,5 +7,8 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
 # Annotate the OpenFPGA architecture to VPR data base
 link_openfpga_arch
 
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --correction --report ./netlist_renaming.rpt
+
 # Finish and exit OpenFPGA
 exit