add check codes for mode bits annotation to pb_types and clean up utils source files
This commit is contained in:
tangxifan
parent
a4381563bc
commit
d2c47693f6
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@ -1019,6 +1019,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
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VTR_LOG("Building annotation between physical pb_types and mode selection bits...\n");
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link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
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vpr_pb_type_annotation);
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check_vpr_pb_type_mode_bits_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
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const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
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}
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@ -8,6 +8,7 @@
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#include "vtr_log.h"
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#include "pb_type_utils.h"
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#include "circuit_library_utils.h"
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#include "check_pb_type_annotation.h"
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/* begin namespace openfpga */
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@ -89,8 +90,8 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
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if (0 == num_err) {
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VTR_LOG("Check physical mode annotation for pb_types passed.\n");
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} else {
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VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
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num_err);
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VTR_LOG_ERROR("Check physical mode annotation for pb_types failed with %ld errors!\n",
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num_err);
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}
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}
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@ -139,10 +140,7 @@ void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
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return;
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}
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/* Traverse all the modes
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* - for pb_type children under a physical mode, we expect an physical mode
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* - for pb_type children under non-physical mode, we expect no physical mode
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*/
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/* Traverse all the modes */
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for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
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for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) {
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rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
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@ -173,8 +171,8 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
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if (0 == num_err) {
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VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
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} else {
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VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
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num_err);
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VTR_LOG_ERROR("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
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num_err);
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}
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}
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@ -274,4 +272,110 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
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}
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}
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/********************************************************************
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* This function will recursively traverse all the primitive pb_types
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* in the graph to ensure
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* - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
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* and the circuit model must have a port for mode selection.
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* And the port size must match the length of mode bits
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*******************************************************************/
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static
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void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
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const CircuitLibrary& circuit_lib,
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const VprPbTypeAnnotation& vpr_pb_type_annotation,
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size_t& num_err) {
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/* Primitive pb_type should always been binded to a physical pb_type */
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if (true == is_primitive_pb_type(cur_pb_type)) {
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/* Find the physical pb_type
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* If the physical pb_type has mode selection bits, this pb_type must have as well!
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*/
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t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(cur_pb_type);
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if (nullptr == physical_pb_type) {
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VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
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cur_pb_type->name);
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VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
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num_err++;
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return;
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}
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if (vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size() != vpr_pb_type_annotation.pb_type_mode_bits(physical_pb_type).size()) {
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VTR_LOG_ERROR("Found different sizes of mode_bits for pb_type '%s' and its physical pb_type '%s'\n",
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cur_pb_type->name,
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physical_pb_type->name);
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num_err++;
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return;
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}
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/* Try to find a mode selection port for the circuit model linked to the circuit model */
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CircuitModelId circuit_model = vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type);
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if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type)) {
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VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
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physical_pb_type->name);
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num_err++;
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return; /* Invalid id already, further check is not applicable */
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}
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if (0 == vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
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/* No mode bits to be checked! */
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return;
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}
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/* Search the ports of this circuit model and we must have a mode selection port */
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std::vector<CircuitPortId> mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, circuit_model);
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size_t port_num_mode_bits = 0;
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for (const CircuitPortId& mode_select_port : mode_select_ports) {
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port_num_mode_bits += circuit_lib.port_size(mode_select_port);
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}
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if (port_num_mode_bits != vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
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VTR_LOG_ERROR("Length of mode bits of pb_type '%s' does not match the size(%ld) of mode selection ports of circuit model '%s'!\n",
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cur_pb_type->name,
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port_num_mode_bits,
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circuit_lib.model_name(circuit_model).c_str());
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num_err++;
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}
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return;
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}
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/* Traverse all the modes */
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for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
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for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) {
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rec_check_vpr_pb_type_mode_bits_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
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circuit_lib, vpr_pb_type_annotation,
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num_err);
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}
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}
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}
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/********************************************************************
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* This function will check the mode_bits annotation for each pb_type
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* - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
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* - If a primitive pb_type has mode bits, the circuit model must have
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* a port for mode selection. And the port size must match the length of mode bits
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*
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* Note:
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* - This function should be run after circuit mode and mode bits annotation
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* is completed
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*******************************************************************/
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void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx,
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const CircuitLibrary& circuit_lib,
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const VprPbTypeAnnotation& vpr_pb_type_annotation) {
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size_t num_err = 0;
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for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
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/* By pass nullptr for pb_type head */
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if (nullptr == lb_type.pb_type) {
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continue;
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}
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/* Top pb_type should always has a physical mode! */
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rec_check_vpr_pb_type_mode_bits_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
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}
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if (0 == num_err) {
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VTR_LOG("Check pb_type annotation for mode selection bits passed.\n");
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} else {
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VTR_LOG_ERROR("Check physical pb_type annotation for mode selection bits failed with %ld errors!\n",
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num_err);
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}
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}
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} /* end namespace openfpga */
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@ -25,6 +25,10 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
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const CircuitLibrary& circuit_lib,
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const VprPbTypeAnnotation& vpr_pb_type_annotation);
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void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx,
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const CircuitLibrary& circuit_lib,
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const VprPbTypeAnnotation& vpr_pb_type_annotation);
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} /* end namespace openfpga */
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#endif
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@ -0,0 +1,229 @@
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/************************************************************************
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* Function to perform fundamental operation for the circuit library
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* These functions are not universal methods for the CircuitLibrary class
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* They are made to ease the development in some specific purposes
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* Please classify such functions in this file
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***********************************************************************/
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#include <algorithm>
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "circuit_library_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Get the model id of a SRAM model that is used to configure
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* a circuit model
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*******************************************************************/
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std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* SRAM model id is stored in the sram ports of a circuit model */
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
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std::vector<CircuitModelId> sram_models;
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/* Create a list of sram models, but avoid duplicated model ids */
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for (const auto& sram_port : sram_ports) {
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CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
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VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
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if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
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continue; /* Already in the list, skip the addition */
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}
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/* Not in the list, add it */
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sram_models.push_back(sram_model);
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}
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return sram_models;
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}
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/********************************************************************
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* Find regular (not mode select) sram ports of a circuit model
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
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std::vector<CircuitPortId> regular_sram_ports;
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for (const auto& port : sram_ports) {
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if (true == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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regular_sram_ports.push_back(port);
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}
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return regular_sram_ports;
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}
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/********************************************************************
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* Find mode select sram ports of a circuit model
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
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std::vector<CircuitPortId> mode_select_sram_ports;
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for (const auto& port : sram_ports) {
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if (false == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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mode_select_sram_ports.push_back(port);
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}
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return mode_select_sram_ports;
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}
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/********************************************************************
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* Find the number of shared configuration bits for a ReRAM circuit
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* TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
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*******************************************************************/
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static
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size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& rram_model,
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const e_config_protocol_type& config_protocol_type) {
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size_t num_shared_config_bits = 0;
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/* Branch on the organization of configuration protocol */
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switch (config_protocol_type) {
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_SCAN_CHAIN:
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break;
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case CONFIG_MEM_MEMORY_BANK: {
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/* Find BL/WL ports */
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std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, CIRCUIT_MODEL_PORT_BLB);
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for (auto blb_port : blb_ports) {
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num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
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}
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break;
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}
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default:
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VTR_LOG_ERROR("Invalid type of configuration protocol!\n");
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exit(1);
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}
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return num_shared_config_bits;
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}
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/********************************************************************
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* A generic function to find the number of shared configuration bits
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* for circuit model
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* It will return 0 for CMOS circuits
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* It will return the maximum shared configuration bits across ReRAM models
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*
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* Note: This function may give WRONG results when all the SRAM ports
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* are not properly linked to its circuit models!
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* So, it should be called after the SRAM linking is done!!!
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*
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* IMPORTANT: This function should NOT be used to find the number of shared configuration bits
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* for a multiplexer, because the multiplexer size is determined during
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* the FPGA architecture generation (NOT during the XML parsing).
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*******************************************************************/
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size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const e_config_protocol_type& config_protocol_type) {
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size_t num_shared_config_bits = 0;
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
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for (auto sram_port : sram_ports) {
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CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
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VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
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/* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
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switch (circuit_lib.design_tech_type(sram_model)) {
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case CIRCUIT_MODEL_DESIGN_CMOS:
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/* CMOS circuit do not need shared configuration bits */
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break;
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case CIRCUIT_MODEL_DESIGN_RRAM:
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/* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
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num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, config_protocol_type));
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break;
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default:
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VTR_LOG_ERROR("Invalid design technology for SRAM circuit model!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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}
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return num_shared_config_bits;
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}
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/********************************************************************
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* A generic function to find the number of configuration bits
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* for circuit model
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* It will sum up the sizes of all the sram ports
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*
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* IMPORTANT: This function should NOT be used to find the number of configuration bits
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* for a multiplexer, because the multiplexer size is determined during
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* the FPGA architecture generation (NOT during the XML parsing).
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*******************************************************************/
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size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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size_t num_config_bits = 0;
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
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for (auto sram_port : sram_ports) {
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num_config_bits += circuit_lib.port_size(sram_port);
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}
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return num_config_bits;
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}
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/********************************************************************
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* A generic function to find all the global ports in a circuit library
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*
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* IMPORTANT: This function will uniquify the global ports whose share
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* share the same name !!!
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) {
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std::vector<CircuitPortId> global_ports;
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for (auto port : circuit_lib.ports()) {
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/* By pass non-global ports*/
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if (false == circuit_lib.port_is_global(port)) {
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continue;
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}
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/* Check if a same port with the same name has already been in the list */
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bool add_to_list = true;
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for (const auto& global_port : global_ports) {
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if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) {
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/* Same name, skip list update */
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add_to_list = false;
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break;
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}
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}
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if (true == add_to_list) {
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/* Add the global_port to the list */
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global_ports.push_back(port);
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}
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}
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return global_ports;
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}
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/********************************************************************
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* A generic function to find all the unique user-defined
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* Verilog netlists in a circuit library
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* Netlists with same names will be considered as one
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*******************************************************************/
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std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) {
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std::vector<std::string> netlists;
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for (const CircuitModelId& model : circuit_lib.models()) {
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/* Skip empty netlist names */
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if (true == circuit_lib.model_verilog_netlist(model).empty()) {
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continue;
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}
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/* See if the netlist name is already in the list */
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std::vector<std::string>::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model));
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if (it == netlists.end()) {
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netlists.push_back(circuit_lib.model_verilog_netlist(model));
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}
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}
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return netlists;
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}
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} /* end namespace openfpga */
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@ -0,0 +1,44 @@
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/********************************************************************
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* Header file for circuit_library_utils.cpp
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*******************************************************************/
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#ifndef CIRCUIT_LIBRARY_UTILS_H
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#define CIRCUIT_LIBRARY_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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||||
*******************************************************************/
|
||||
|
||||
#include <vector>
|
||||
#include "circuit_types.h"
|
||||
#include "circuit_library.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
|
||||
const CircuitModelId& circuit_model);
|
||||
|
||||
std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
|
||||
const CircuitModelId& circuit_model);
|
||||
|
||||
std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
|
||||
const CircuitModelId& circuit_model);
|
||||
|
||||
size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
|
||||
const CircuitModelId& circuit_model,
|
||||
const e_config_protocol_type& sram_orgz_type);
|
||||
|
||||
size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
|
||||
const CircuitModelId& circuit_model);
|
||||
|
||||
std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
|
||||
|
||||
std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue