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OpenFPGA
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2,634 Commits 71 Branches 8 Tags 105 MiB
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481 Commits

Author SHA1 Message Date
tangxifan 49d6863641 [Architecture] Bug fix for scan-chain FF cell renaming 2020-09-24 17:33:14 -06:00
tangxifan 0a5369f919 [Architecture] Adapt all the architecture files to use standard DFF cell 2020-09-24 17:26:48 -06:00
tangxifan 19dd3778d9 [Architecture] Add test case for memory bank to use both reset and set 2020-09-24 17:04:24 -06:00
tangxifan 335f5b78c1 [Regression Test] Add test case to use both set and reset for configuration frame 2020-09-24 17:02:28 -06:00
tangxifan 2d81ff9012 [Regression test] Add configuration chain test case where both set and reset are used 2020-09-24 16:59:52 -06:00
tangxifan fc154b8560 [Architecture] Bug fix due to switching CCFF cell 2020-09-24 16:45:56 -06:00
tangxifan 79875d5a91 [Architecture] Bug fix in the configuration chain arch using both reset and set 2020-09-24 15:27:26 -06:00
tangxifan 9cb67e6097 [Architecture] Now all the configuration chain architecture use the DFFR cell by default 2020-09-24 15:19:37 -06:00
tangxifan 81965e75f6 [Architecture] Bug fix in DFF Verilog HDL 2020-09-24 14:53:21 -06:00
tangxifan 3b42fe94d6 [Architecture] Update external bitstream file 2020-09-24 14:41:44 -06:00
tangxifan 7fbccdd102 [Regression Tests] Add test cases for configuration chain using different DFF cells 2020-09-24 14:34:12 -06:00
tangxifan 178afb3c7f [Architecture] Add configuration chain architectures using different DFF cells 2020-09-24 14:23:27 -06:00
tangxifan 98d88dc686 [Architecture] Bug fix for vanilla memory organization 2020-09-24 14:13:48 -06:00
tangxifan efad0402c2 [Regression Test] Bug fix for CI errors 2020-09-24 13:55:41 -06:00
tangxifan e7906899dd [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset 2020-09-24 13:53:12 -06:00
tangxifan e832d806c7 [Architecture] Add DFF Verilog netlist using standard naming convention 2020-09-24 13:50:59 -06:00
tangxifan 1b13e8ecb1 [Architecture] Bug fix in the SRAM Verilog 2020-09-24 12:26:13 -06:00
tangxifan ffd1a72d22 [Architecture] Add regression tests for the frame-based configuration using reset and set signals 2020-09-24 12:18:26 -06:00
tangxifan 539bb617f9 [Architecture] Add reset test case for frame based configuration 2020-09-24 12:17:18 -06:00
tangxifan 2add0406a7 [Architecture] Update architecture files for new latch naming 2020-09-24 12:14:03 -06:00
tangxifan fde15c4f88 [Regression Test] Add test for fast memory bank configuration using set signals 2020-09-24 12:13:35 -06:00
tangxifan 7238a2be03 [Architecture] Merge latch Verilog HDL to a unique file 2020-09-24 11:02:01 -06:00
tangxifan 48083d2276 [Regression Test] Adapt fast memory bank test case 2020-09-24 10:32:03 -06:00
tangxifan 83971bba41 [Architecture] Update cell ports for native SRAM cell 2020-09-24 10:31:31 -06:00
tangxifan 186f00edfc [Regression Test] Add test cases for memory bank using different SRAM cells 2020-09-24 10:25:03 -06:00
tangxifan 56c9aab190 [Architecture] Add architecture to use different SRAM cells for memory bank 2020-09-24 10:15:08 -06:00
tangxifan 6bb30ab33c [Architecture] Enrich SRAM Verilog HDL for flexible set/reset support 2020-09-24 10:02:51 -06:00
tangxifan 10b6e1dc0d [Architecture] bug fix for active-low 2020-09-23 23:06:46 -06:00
tangxifan 5b0d451f0f [Regression Test] Add test case for configurable latch with active-low set 2020-09-23 23:04:10 -06:00
tangxifan 5d60b4ef8c [Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set 2020-09-23 23:02:49 -06:00
tangxifan 8e780635df [Regression Test] Rename test case in CI 2020-09-23 22:59:46 -06:00
tangxifan d0cef68242 [Regression test] Add test case for using resetb 2020-09-23 22:58:59 -06:00
tangxifan c7fc0178b0 [Architecture] Rename to be consist with other architectures 2020-09-23 22:57:06 -06:00
tangxifan 707300a6e4 [Architecture] Bug fix for using both reset and set architecture 2020-09-23 22:07:40 -06:00
tangxifan 77a1f99564 [Architecture] Bug fix for architecture using set only 2020-09-23 22:04:24 -06:00
tangxifan fcf1ff418f [Architecture] Add Verilog for SRAM using set/reset 2020-09-23 21:53:38 -06:00
tangxifan 73e59d67af [Architecture] Add test case for fast configuration using set signals 2020-09-23 21:50:23 -06:00
tangxifan 349aa79069 [Regression test] Add test case for smart fast configuration 2020-09-23 21:49:38 -06:00
tangxifan 9331ef941d [Architecture] Add architecture that use both set and reset signals 2020-09-23 21:46:04 -06:00
tangxifan 7591060fbd [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
tangxifan 8fa4fa1125 [Architecture] Add openfpga architecture using set signals for configurable latch 2020-09-23 21:39:31 -06:00
tangxifan 05c2e652a4 [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol 2020-09-23 20:44:06 -06:00
tangxifan 2869eae8a9 [Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol 2020-09-23 20:43:15 -06:00
tangxifan fc60b18191 [Architecture] Now a regular flip-flop can be used in frame-based configuration 2020-09-23 20:41:49 -06:00
tangxifan 8e4e66038a [Architecture] Bug fix for standalone memory 2020-09-23 19:32:48 -06:00
tangxifan 129caea38c [Architecture] Patch configurable latch Verilog HDL with resetb 2020-09-23 18:30:48 -06:00
tangxifan 1864b080a2 [Architecture] Bug fix in configurable latch Verilog HDL 2020-09-23 18:28:45 -06:00
tangxifan ebb866d04a [Architecture] Patch frame based using ccff 2020-09-23 18:04:14 -06:00
tangxifan 906191e931 [Architecture] Use strict latch Verilog HDL in frame-based procotol 2020-09-23 17:58:13 -06:00
tangxifan 645db17168 [Architecture] Patch DFF Verilog HDL 2020-09-23 17:52:59 -06:00
tangxifan 092ada39f4 [Architecture] Add Verilog HDL for DFF with write enable 2020-09-23 17:49:30 -06:00
tangxifan ad385c6d69 [Regression Test] Add test case for using SRAM cell in frame-based configuration 2020-09-23 17:39:36 -06:00
tangxifan 1a2c66f07d [Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell 2020-09-23 17:34:49 -06:00
tangxifan a3c982a83f [Architecture] Patch the openfpga architecture using active-low configurable latch 2020-09-23 17:27:16 -06:00
tangxifan f23c25e123 [Regression Test] Add test case for configurable latch with active-low reset 2020-09-23 17:25:17 -06:00
tangxifan a94c2655c2 [Architecture] Patch Verilog HDL for configurable latch 2020-09-23 17:21:30 -06:00
tangxifan 893859be37 [Architecture] Add openfpga architecture using active-low configurable latch 2020-09-23 17:21:00 -06:00
tangxifan b242ab79bd [OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset 2020-09-23 17:19:02 -06:00
tangxifan 149d5b20bd [Regression Test] Add test case for fixed device support 2020-09-23 16:47:11 -06:00
tangxifan c92cf71891 [Regression Test] Add a new template script for fixed device support 2020-09-23 16:46:41 -06:00
tangxifan 3350695806 [Regression test] Add test case for pattern based local routing architecture 2020-09-23 16:06:47 -06:00
tangxifan 1aab691e9d [Architecture] Add openfpga architecture using pattern based local routing 2020-09-23 16:06:16 -06:00
tangxifan 951a47b19c [Architecture] Add k4 series architecture using pattern-based local routing 2020-09-23 16:05:39 -06:00
tangxifan 7729f671ab [Regression Tests] Remove deadlink 2020-09-22 18:35:41 -06:00
tangxifan 51c0319657 [Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:54 -06:00
tangxifan 70b8b02f74 [Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:11 -06:00
tangxifan 72749be4bd [Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:31:34 -06:00
tangxifan 61bcbaafd8 [Architecture] Add Verilog HDL for fracturable 32-bit multiplier 2020-09-22 15:15:19 -06:00
tangxifan 3d1f49fb2f [Regression Test] Add testcase for k4n4 with multiple segments 2020-09-22 12:47:41 -06:00
tangxifan 13df6c1c21 [Architecture] Add openfpga architecture for k4n4 using multiple segments 2020-09-22 12:36:11 -06:00
tangxifan 8a3934b749 [Architecture Add vpr architecture for k4n4 using multiple wire segments 2020-09-22 12:35:39 -06:00
tangxifan 5741664580 [Regression Test] Add test case for k4n4 bram architecture 2020-09-22 12:23:56 -06:00
tangxifan ddf999b6b9 [Architecture] Add verilog HDL for dual-port BRAM 1k 2020-09-22 12:23:28 -06:00
tangxifan 26fba4a94b [Architecture] Add openfpga architectue for k4n4 with bram blocks 2020-09-22 12:22:59 -06:00
tangxifan daf776b7b1 [Architecture] Add k4n4 architecture with bram block for basic tests 2020-09-22 12:22:32 -06:00
tangxifan 3bf94b8e34 [Regression test] Remove no local routing from fpga verilog tests 2020-09-22 11:48:19 -06:00
tangxifan 7ed9f76b06 [Regression test] Move k4n4 no local routing to basic test 2020-09-22 11:47:03 -06:00
tangxifan 2dea97afb6 [Regression test] reduce runtime for k4n4 test in basic testing 2020-09-22 11:45:29 -06:00
tangxifan ea4dd410b7 [Regression Test] Add k4n4 fracturable lut test case to basic test 2020-09-22 11:41:36 -06:00
tangxifan dad19cac9a [Regression test] Add k4 series architecture: fracturable adder 2020-09-22 11:39:18 -06:00
tangxifan dd192a2f54 [Architecture] Add a k4k4 openfpga architecture with carry chain for quick test 2020-09-22 11:34:23 -06:00
tangxifan 7a6f5a06f7 [Architecture] Add a k4n4 architecture with carry chain to quick test 2020-09-22 11:33:56 -06:00
tangxifan aa5f5fc7e0 [Architecture] Bring back pin equivalence for no local routing architecture 2020-09-21 22:22:39 -06:00
tangxifan a8a269aa82 [Architecture] Temporary patch for the no local routing architecture 2020-09-21 19:51:23 -06:00
tangxifan acf318f184 [Regression test] Bug fix in test case fabric_chain 2020-09-21 18:58:35 -06:00
tangxifan e4291eb27e [Regression Tests] Now use fixed device layout in test cases for best coverage 2020-09-21 18:44:13 -06:00
tangxifan 7a57cc9cf4 [Architecture] A new device layout to k4n4 to test untileable architecture 2020-09-21 18:36:50 -06:00
tangxifan 2bbfcb5753 [Architecture] Add a new device layout to k4n4 for testing tileable routing 2020-09-21 18:34:31 -06:00
tangxifan e1c5947143 [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
tangxifan 936a164eee [OpenFPGA flow] Add a new template script to use a fixed device layout 2020-09-21 17:48:28 -06:00
tangxifan d7f8b3abad [Architecture] Add k4 N4 untilable architecture 2020-09-21 17:44:37 -06:00
tangxifan a83bc3f75c [Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI 2020-09-21 17:38:16 -06:00
tangxifan e9c0e90544 [Architecture] Add a VPR architectue using fracturable LUT4 2020-09-21 17:37:26 -06:00
tangxifan 60f328a2ab [Architecture] Add openfpga architecture for a small k4 fracturable FPGA 2020-09-21 17:36:57 -06:00
tangxifan 681e80d4b6 [Regression tests] update frac_lut test case using more representative benchmarks 2020-09-17 10:39:22 -06:00
tangxifan 367cf59efd [Benchmark] Bug fix in the and2_or2 benchmark 2020-09-17 10:35:13 -06:00
tangxifan de48b8c7b2 [Benchmark] Add a new micro benchmark to test fracturable LUTs 2020-09-17 10:21:25 -06:00
tangxifan ca1bafc688 [OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture 2020-09-16 19:26:12 -06:00
tangxifan c22d8e2421 [Architecture] Bug fix in no local routing architecture 2020-09-16 18:07:52 -06:00
tangxifan c40c9f5876 [Regression test] add test case for no local routing architecture 2020-09-16 18:05:33 -06:00