a3d070ac6f
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
2022-09-12 10:43:21 -07:00
314f5395b4
[benchmark] fixed a bug which causes yosys failed
2022-09-09 17:04:59 -07:00
7a38c7dd18
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
2022-09-09 16:42:55 -07:00
9c7868cfab
[hdl] add a counter design which is triggered by negative edges
2022-05-09 16:41:21 +08:00
430580f138
[HDL] Fix a typo
2022-02-15 16:09:14 -08:00
a7786efde1
[HDL] Now dual-clock counter has only 1 reset pin
2022-02-15 16:07:50 -08:00
7121513396
[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
2022-02-15 15:21:08 -08:00
48355d1fc3
[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers
2022-01-02 20:16:59 -08:00
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
5a6874e9f1
[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
2021-07-02 17:28:17 -06:00
0b6a9b06f5
[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
2021-07-02 10:39:07 -06:00
1d281765ea
fixed tab spacing
2021-07-01 16:42:04 -06:00
808821bb8c
fixed errors
2021-07-01 16:40:03 -06:00
8513b8a4ff
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
2021-07-01 15:29:39 -06:00
2567fbee05
ready to merge
2021-07-01 15:28:59 -06:00
04ceeefb0a
Merge branch 'master' into verilog_testbench
2021-07-01 14:43:26 -06:00
db9231c225
tests failing with initial blocks
2021-07-01 13:52:28 -06:00
fab2b069f0
added signal gen regression test to shell script
2021-06-30 16:18:09 -06:00
a898537474
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
2021-06-30 15:29:13 -06:00
4d4577bb83
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00
477cba1c7e
Merge branch 'master' into verilog_testbench
2021-06-23 09:18:18 -06:00
0a0d10b36d
[HDL] Bug fix in Verilog syntax
2021-06-22 16:18:46 -06:00
07dcf3ad27
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
2021-06-21 16:48:35 -06:00
3cfc42cdf9
added testbench CI
2021-06-15 14:16:31 -06:00
16fff90607
[Benchmark] Add microbenchmark 1-bit blinking
2021-05-06 15:17:27 -06:00
a571b063b6
[Benchmark] Add 1k DPRAM benchmark which can fit new arch
2021-04-28 11:26:31 -06:00
7d059f7407
[Benchmark] Bug fix in dual port ram 16k benchmark
2021-04-27 23:33:20 -06:00
3c1c33bf1e
[Benchmark] Add a microbenchmark just fit 16k dual port ram
2021-04-27 22:51:43 -06:00
7e2368158e
[Benchmark] move benchmarks to microbenchmark category
2021-04-27 22:12:30 -06:00
5a85ec9fa0
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
2021-04-27 22:09:10 -06:00
1d498bb296
[Benchmark] Add a scalable micro benchmark fifo
2021-04-27 15:26:52 -06:00
200b6d39a6
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
2021-04-23 20:36:28 -06:00
671394ec2c
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
2021-04-23 20:33:43 -06:00
b203ef7bc2
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
2021-04-21 14:03:51 -06:00
bbdc0e53af
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
2021-04-16 20:14:48 -06:00
be03eafd66
[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
2021-03-23 15:33:37 -06:00
1f097abe99
[Benchmark] Add micro benchmark for FIR filter
2021-02-18 19:37:44 -07:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
tangxifan
Aram Kostanyan
ANDREW HARRIS POND
Andrew Pond
AurelienAlacchi