AurelienUoU
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3b13c959f3
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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AurelienUoU
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c4449b667f
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-26 11:34:59 -06:00 |
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AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
tangxifan
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ea0da49e04
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Merge branch 'dev' into refactoring
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2019-09-25 21:06:06 -06:00 |
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tangxifan
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5bb40e7f74
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refactored local wire generation for Switch block
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2019-09-25 21:05:02 -06:00 |
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AurelienUoU
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e5faeb1400
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-25 16:50:53 -06:00 |
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AurelienUoU
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a35e2936b2
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Fix verilog generation for direct connexion from directlist
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2019-09-25 16:44:00 -06:00 |
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tangxifan
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2b0e2615fa
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refactored sram port addition to module manager
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2019-09-25 16:09:58 -06:00 |
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tangxifan
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c911f15a67
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add formal verification port to SB Verilog generation
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2019-09-23 21:15:45 -06:00 |
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tangxifan
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e1742b68ef
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add pre-processing flag support for module manager
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2019-09-23 20:25:53 -06:00 |
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tangxifan
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d2ddbc19a3
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refactoring the reserved sram port generation
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2019-09-22 16:38:16 -06:00 |
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tangxifan
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2c4372c506
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add reserved BLB/WL port naming
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2019-09-22 12:16:43 -06:00 |
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tangxifan
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1e4177067d
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remove port size in the module definition
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2019-09-22 11:21:43 -06:00 |
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tangxifan
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0ff0c8cf06
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bug fix for IO=1
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2019-09-19 15:43:25 -06:00 |
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tangxifan
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e0b253d30a
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minor fix for non-LUT intermedate buffer case
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2019-09-18 15:15:03 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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2294aecef2
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remove old codes and compact new codes
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2019-09-16 20:19:14 -06:00 |
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tangxifan
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c5ee81541a
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remove dead codes in routing module generation
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2019-09-16 18:47:01 -06:00 |
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tangxifan
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0963852091
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remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
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2019-09-16 18:38:37 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
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tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
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b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |
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tangxifan
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0e6c88dd52
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delete legacy codes for wire Verilog generation
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2019-09-12 21:06:53 -06:00 |
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tangxifan
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c20e182484
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plugged in the refactored wire Verilog generation
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2019-09-12 20:56:30 -06:00 |
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tangxifan
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2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
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0711aa1bd6
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minor bug fixing
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2019-09-10 16:56:14 -06:00 |
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tangxifan
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82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
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5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |