Ganesh Gore
|
1c4acff79b
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-11-15 14:54:13 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
|
2019-11-15 14:35:15 -07:00 |
|
Ganesh Gore
|
333d10c94c
|
Added vpr_fpga_verilog_print_simulation_ini option
|
2019-11-15 14:26:57 -07:00 |
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
0c2ad5ab5e
|
critical bug fixed for some corner cases
|
2019-11-13 20:45:41 -07:00 |
|
tangxifan
|
1291b99d66
|
now make ini file generation more flexible: user can specify a name or use the default name
|
2019-11-13 12:55:57 -07:00 |
|
tangxifan
|
d84cd66287
|
refactored analysis SDC generator for grids
|
2019-11-12 22:18:13 -07:00 |
|
tangxifan
|
6c58a4dd92
|
refactored unused grid block SDC analysis generation
|
2019-11-12 10:01:17 -07:00 |
|
tangxifan
|
8a57a29d2d
|
refactoring analysis SDC generation for grids
|
2019-11-11 22:38:11 -07:00 |
|
tangxifan
|
5f219b428c
|
refactored analysis SDC generation for switch blocks
|
2019-11-11 19:24:39 -07:00 |
|
tangxifan
|
876733f052
|
now we use module manager to generate analysis SDC, being independent from VPR structures
|
2019-11-10 21:15:34 -07:00 |
|
tangxifan
|
a849522be9
|
refactored CB SDC analysis generation
|
2019-11-10 20:15:16 -07:00 |
|
tangxifan
|
8e8e59b0ca
|
give specific name to mux so that we can bind it to SDC generator
|
2019-11-10 19:42:30 -07:00 |
|
tangxifan
|
3d711823e5
|
refactoring SDC generator for unused CBs
|
2019-11-10 18:15:13 -07:00 |
|
tangxifan
|
67b3b25bea
|
refactoring analysis sdc generation
|
2019-11-10 16:08:49 -07:00 |
|
tangxifan
|
1f368abfbe
|
refactoring analysis SDC generation
|
2019-11-10 15:40:54 -07:00 |
|
tangxifan
|
bcd8237263
|
refactored grid PnR SDC generator
|
2019-11-09 20:57:54 -07:00 |
|
tangxifan
|
d226d18d40
|
move SDC generator for routing modules to an independent source file
|
2019-11-09 11:54:05 -07:00 |
|
tangxifan
|
a7f2a61d0d
|
refactored CB SDC generation
|
2019-11-09 11:42:38 -07:00 |
|
tangxifan
|
4b5ecc516b
|
refactored SDC SB constrain generation
|
2019-11-09 10:52:15 -07:00 |
|
tangxifan
|
be574b0d45
|
refactored disable routing mux outputs
|
2019-11-08 19:05:05 -07:00 |
|
tangxifan
|
e273c00c9d
|
add refactored disable timing for memory cells
|
2019-11-08 17:38:07 -07:00 |
|
tangxifan
|
ea7c981c85
|
critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
|
2019-11-08 15:01:30 -07:00 |
|
tangxifan
|
33b3705ced
|
refactoring disable outputs sdc generation
|
2019-11-08 11:15:35 -07:00 |
|
tangxifan
|
35e718b32d
|
rename backend sdc generator to be backend assistant
|
2019-11-08 10:20:12 -07:00 |
|
tangxifan
|
14e7744fee
|
start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
|
2019-11-07 22:20:48 -07:00 |
|
tangxifan
|
d391983e8c
|
passing regression test on dpram benchmarks
|
2019-11-07 14:57:46 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
09eb373a6e
|
bug fixing for autocheck top testbench where clock port is not default names
|
2019-11-06 12:21:20 -07:00 |
|
tangxifan
|
0e620f35a4
|
bug fixed for MUX2 std cells, avoid duplicated module writing
|
2019-11-06 11:45:28 -07:00 |
|
tangxifan
|
aac4ccb279
|
fixing bug for heterogeneous FPGAs
|
2019-11-06 11:19:17 -07:00 |
|
tangxifan
|
6c04b8d959
|
bug fixing for heterogeneous FPGAs
|
2019-11-05 20:24:03 -07:00 |
|
tangxifan
|
066962fbb9
|
bug fixed for clb2clb direct connection
|
2019-11-05 17:41:21 -07:00 |
|
tangxifan
|
227fb9a1a5
|
clean up the support for std cells
|
2019-11-05 17:32:05 -07:00 |
|
tangxifan
|
aa56d95073
|
bug fixed for using standard cells
|
2019-11-05 17:19:57 -07:00 |
|
tangxifan
|
00280b835e
|
reorganize regression tests
|
2019-11-05 16:31:42 -07:00 |
|
tangxifan
|
7952d134b9
|
add tree-like mux test case to regression test
|
2019-11-05 16:24:39 -07:00 |
|
tangxifan
|
696d4a9522
|
remove useless channel wire module generation
|
2019-11-05 16:10:00 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
|
tangxifan
|
2fbb88d25b
|
remove legacy codes
|
2019-11-05 13:52:42 -07:00 |
|
tangxifan
|
66047e4a45
|
refactoring Verilog simulation flag generations
|
2019-11-05 13:45:11 -07:00 |
|
tangxifan
|
13f2d33d37
|
refactored fpga_define.v generation
Please enter the commit message for your changes. Lines starting
|
2019-11-05 12:41:43 -07:00 |
|
tangxifan
|
8ef9e994d8
|
rename source files to be what they are actually doing
|
2019-11-05 12:18:23 -07:00 |
|
tangxifan
|
aaaf7a0d19
|
remove legacy codes in writing include netlists
|
2019-11-04 21:06:14 -07:00 |
|
tangxifan
|
ebab0e91ef
|
refactored include netlist writer
|
2019-11-04 20:55:30 -07:00 |
|
tangxifan
|
5d507ae8ee
|
bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
|
tangxifan
|
69bc858e62
|
bring autocheck top testbench back to simulation deck, start testing
|
2019-11-04 15:35:04 -07:00 |
|
tangxifan
|
3274a49779
|
fine tuning top testbench and getting ready for testing
|
2019-11-04 12:08:36 -07:00 |
|
tangxifan
|
d7bbae76a4
|
adding stimuli to benchmark inputs in top-level testbench
|
2019-11-03 20:20:14 -07:00 |