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critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer

This commit is contained in:
tangxifan 2019-11-08 15:01:30 -07:00
parent 33b3705ced
commit ea7c981c85
3 changed files with 32 additions and 22 deletions
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6
vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp
View File

@ -248,7 +248,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager
/* No bitstream generation required by a special direct connection*/
} else if (1 < src_rr_node->fan_in) {
/* Create the block denoting the memory instances that drives this node in Switch Block */
std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), src_rr_node->ptc_num, std::string(""));
std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string(""));
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block);
/* This is a routing multiplexer! Generate bitstream */
@ -380,13 +380,13 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager,
* To organize the bitstream in blocks, we create a block for each connection block
* and give names which are same as they are in top-level module managers
*/
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-directionConnection blocks ...\n");
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-direction Connection blocks ...\n");
build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,
circuit_lib, mux_lib, rr_switches, L_rr_node,
L_device_rr_gsb, CHANX);
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-directionConnection blocks ...\n");
vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-direction Connection blocks ...\n");
build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,
circuit_lib, mux_lib, rr_switches, L_rr_node,

2
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp
View File

@ -780,7 +780,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
/* Give an instance name: this name should be consistent with the block name given in bitstream manager,
* If you want to bind the bitstream generation to modules
*/
std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), cur_rr_node->ptc_num, std::string(""));
std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string(""));
module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name);
/* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */

46
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
View File

@ -95,9 +95,9 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag
* to write up local wire declaration in Verilog format
*******************************************************************/
static
std::vector<BasicPort> find_verilog_module_local_wires(const ModuleManager& module_manager,
const ModuleId& module_id) {
std::vector<BasicPort> local_wires;
std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(const ModuleManager& module_manager,
const ModuleId& module_id) {
std::map<std::string, std::vector<BasicPort>> local_wires;
/* Local wires come from the child modules */
for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
@ -119,20 +119,28 @@ std::vector<BasicPort> find_verilog_module_local_wires(const ModuleManager& modu
}
/* Find the name for this local wire */
BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net);
/* Try to find a port in the list that can absorb the current local wire */
/* Cache the net name, try to find it in the cache.
* If you can find one, it means this port may be mergeable, try to do merging. If merge fail, add to the local wire list
* If you cannot find one, it means that this port is not mergeable, add to the local wire list immediately.
*/
std::map<std::string, std::vector<BasicPort>>::iterator it = local_wires.find(local_wire_candidate.get_name());
bool merged = false;
for (BasicPort& local_wire : local_wires) {
/* check if the candidate can be combined to an existing local wire */
if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) {
/* Merge the ports */
local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate);
merged = true;
break;
}
if (it != local_wires.end()) {
/* Try to merge to one the port in the list that can absorb the current local wire */
for (BasicPort& local_wire : local_wires[local_wire_candidate.get_name()]) {
/* check if the candidate can be combined to an existing local wire */
if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) {
/* Merge the ports */
local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate);
merged = true;
break;
}
}
}
/* If not merged, push the port to the list */
/* If not merged/not found in the cache, push the port to the list */
if (false == merged) {
local_wires.push_back(local_wire_candidate);
local_wires[local_wire_candidate.get_name()].push_back(local_wire_candidate);
}
}
@ -161,7 +169,7 @@ std::vector<BasicPort> find_verilog_module_local_wires(const ModuleManager& modu
instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
*std::max_element(undriven_pins.begin(), undriven_pins.end()));
local_wires.push_back(instance_port);
local_wires[instance_port.get_name()].push_back(instance_port);
}
}
}
@ -436,9 +444,11 @@ void write_verilog_module_to_file(std::fstream& fp,
fp << std::endl;
/* Print internal wires */
std::vector<BasicPort> local_wires = find_verilog_module_local_wires(module_manager, module_id);
for (BasicPort local_wire : local_wires) {
fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl;
std::map<std::string, std::vector<BasicPort>> local_wires = find_verilog_module_local_wires(module_manager, module_id);
for (std::pair<std::string, std::vector<BasicPort>> port_group : local_wires) {
for (const BasicPort& local_wire : port_group.second) {
fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl;
}
}
/* Print an empty line as splitter */