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refactoring disable outputs sdc generation

This commit is contained in:
tangxifan 2019-11-08 11:15:35 -07:00
parent 35e718b32d
commit 33b3705ced
5 changed files with 117 additions and 21 deletions
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64
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp
View File

@ -43,7 +43,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const std::vector<CircuitPortId>& global_ports) {
/* Create the file name for Verilog netlist */
std::string sdc_fname(sdc_dir + std::string(SDC_CLOCK_FILE_NAME));
std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
vpr_printf(TIO_MESSAGE_INFO,
"Generating SDC for constraining clocks for P&R flow: %s ...",
@ -138,6 +138,47 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
run_time_sec);
}
/********************************************************************
* Break combintational loops in FPGA fabric, which mainly come from:
* 1. Configurable memory cells.
* To handle this, we disable the outputs of memory cells
* 2. Loops of multiplexers.
* To handle this, we disable the outputs of routing multiplexers
*******************************************************************/
static
void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir) {
/* Create the file name for Verilog netlist */
std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME));
vpr_printf(TIO_MESSAGE_INFO,
"Generating SDC for disable configurable memory outputs for P&R flow: %s ...",
sdc_fname.c_str());
/* Start time count */
clock_t t_start = clock();
/* Create the file stream */
std::fstream fp;
fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
check_file_handler(fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("disable configurable memory outputs for PnR"));
/* Close file handler */
fp.close();
/* End time count */
clock_t t_end = clock();
float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO,
"took %g seconds\n",
run_time_sec);
}
/********************************************************************
* Top-level function to print a number of SDC files in different purpose
* This function will generate files upon the options provided by users
@ -155,4 +196,25 @@ void print_pnr_sdc(const SdcOption& sdc_options,
if (true == sdc_options.constrain_global_port()) {
print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
}
/* Part 2. Output Design Constraints to disable outputs of memory cells */
if (true == sdc_options.constrain_configurable_memory_outputs()) {
print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir());
}
/* 2. Break loops from Multiplexer Output */
/*
if (TRUE == sdc_opts.break_loops_mux) {
verilog_generate_sdc_break_loop_mux(fp, num_switch, switches, spice, routing_arch);
}
*/
/* TODO: 3. Break loops from any SB output */
/*
if (TRUE == sdc_opts.compact_routing_hierarchy) {
verilog_generate_sdc_break_loop_sb(fp, LL_device_rr_gsb);
} else {
verilog_generate_sdc_break_loop_sb(fp, LL_nx, LL_ny);
}
*/
}

55
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp
View File

@ -8,14 +8,15 @@
********************************************************************/
SdcOption::SdcOption(const std::string& sdc_dir) {
sdc_dir_ = sdc_dir;
constrain_global_port_ = true;
constrain_grid_ = true;
constrain_sb_ = true;
constrain_cb_ = true;
break_loop_ = true;
constrain_global_port_ = false;
constrain_grid_ = false;
constrain_sb_ = false;
constrain_cb_ = false;
constrain_configurable_memory_outputs_ = false;
constrain_routing_multiplexer_outputs_ = false;
constrain_switch_block_outputs_ = false;
}
/********************************************************************
* Public accessors
********************************************************************/
@ -24,11 +25,17 @@ std::string SdcOption::sdc_dir() const {
}
bool SdcOption::generate_sdc() const {
return generate_sdc_pnr_ && generate_sdc_analysis_;
return generate_sdc_pnr() && generate_sdc_analysis_;
}
bool SdcOption::generate_sdc_pnr() const {
return generate_sdc_pnr_;
return constrain_global_port_
|| constrain_grid_
|| constrain_sb_
|| constrain_cb_
|| constrain_configurable_memory_outputs_
|| constrain_routing_multiplexer_outputs_
|| constrain_switch_block_outputs_;
}
bool SdcOption::generate_sdc_analysis() const {
@ -51,8 +58,16 @@ bool SdcOption::constrain_cb() const {
return constrain_cb_;
}
bool SdcOption::break_loop() const {
return break_loop_;
bool SdcOption::constrain_configurable_memory_outputs() const {
return constrain_configurable_memory_outputs_;
}
bool SdcOption::constrain_routing_multiplexer_outputs() const {
return constrain_routing_multiplexer_outputs_;
}
bool SdcOption::constrain_switch_block_outputs() const {
return constrain_switch_block_outputs_;
}
/********************************************************************
@ -63,7 +78,13 @@ void SdcOption::set_sdc_dir(const std::string& sdc_dir) {
}
void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
generate_sdc_pnr_ = generate_sdc_pnr;
constrain_global_port_ = generate_sdc_pnr;
constrain_grid_ = generate_sdc_pnr;
constrain_sb_ = generate_sdc_pnr;
constrain_cb_ = generate_sdc_pnr;
constrain_configurable_memory_outputs_ = generate_sdc_pnr;
constrain_routing_multiplexer_outputs_ = generate_sdc_pnr;
constrain_switch_block_outputs_ = generate_sdc_pnr;
}
void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
@ -86,7 +107,15 @@ void SdcOption::set_constrain_cb(const bool& constrain_cb) {
constrain_cb_ = constrain_cb;
}
void SdcOption::set_break_loop(const bool& break_loop) {
break_loop_ = break_loop;
void SdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) {
constrain_configurable_memory_outputs_ = constrain_config_mem_outputs;
}
void SdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) {
constrain_routing_multiplexer_outputs_ = constrain_routing_mux_outputs;
}
void SdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) {
constrain_switch_block_outputs_ = constrain_sb_outputs;
}

13
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h
View File

@ -19,7 +19,9 @@ class SdcOption {
bool constrain_grid() const;
bool constrain_sb() const;
bool constrain_cb() const;
bool break_loop() const;
bool constrain_configurable_memory_outputs() const;
bool constrain_routing_multiplexer_outputs() const;
bool constrain_switch_block_outputs() const;
public: /* Public mutators */
void set_sdc_dir(const std::string& sdc_dir);
void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
@ -28,15 +30,18 @@ class SdcOption {
void set_constrain_grid(const bool& constrain_grid);
void set_constrain_sb(const bool& constrain_sb);
void set_constrain_cb(const bool& constrain_cb);
void set_break_loop(const bool& break_loop);
void set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs);
void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs);
void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs);
private: /* Internal data */
std::string sdc_dir_;
bool generate_sdc_pnr_;
bool constrain_global_port_;
bool constrain_grid_;
bool constrain_sb_;
bool constrain_cb_;
bool break_loop_;
bool constrain_configurable_memory_outputs_;
bool constrain_routing_multiplexer_outputs_;
bool constrain_switch_block_outputs_;
bool generate_sdc_analysis_;
};

4
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h
View File

@ -1,9 +1,9 @@
#ifndef SDC_WRITER_NAMING_H
#define SDC_WRITER_NAMING_H
constexpr char* SDC_CLOCK_FILE_NAME = "clb_clock.sdc";
constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc";
constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc";
constexpr char* SDC_BREAK_COMB_LOOP_FILE_NAME = "break_loop.sdc";
constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc";
constexpr char* SDC_CB_FILE_NAME = "cb.sdc";
constexpr char* SDC_SB_FILE_NAME = "sb.sdc";

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c
View File

@ -151,7 +151,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
src_dir = format_dir_path(src_dir);
}
SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR)));
sdc_options.set_generate_sdc_pnr(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr);
sdc_options.set_generate_sdc_pnr(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr);
sdc_options.set_generate_sdc_analysis(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis);
if (true == sdc_options.generate_sdc()) {