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now make ini file generation more flexible: user can specify a name or use the default name

This commit is contained in:
tangxifan 2019-11-13 12:55:57 -07:00
parent d84cd66287
commit 1291b99d66
7 changed files with 47 additions and 13 deletions
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1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -101,6 +101,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_simulation_ini_file", OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE }, /* Specify the simulator path for Verilog netlists */
/* Xifan Tang: Bitstream generator */
{ "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */
// { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -118,6 +118,7 @@ enum e_OptionBaseToken {
OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR,
OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS,
OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI,
OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE,
/* Xifan Tang: Bitstream generator */
OT_FPGA_BITSTREAM_GENERATOR,
OT_FPGA_BITSTREAM_OUTPUT_FILE,

2
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -560,6 +560,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI:
return Args;
case OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE:
return ReadString(Args, &Options->fpga_verilog_simulation_ini_path);
/* Xifan TANG: Bitstream generator */
case OT_FPGA_BITSTREAM_GENERATOR:

6
vpr7_x2p/vpr/SRC/base/SetupVPR.c
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@ -1114,6 +1114,7 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->print_sdc_analysis = FALSE;
syn_verilog_opts->include_icarus_simulator = FALSE;
syn_verilog_opts->print_simulation_ini = FALSE;
syn_verilog_opts->simulation_ini_path = NULL;
/* Turn on Syn_verilog options */
if (Options.Count[OT_FPGA_VERILOG_SYN]) {
@ -1186,7 +1187,10 @@ static void SetupSynVerilogOpts(t_options Options,
if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) {
syn_verilog_opts->print_simulation_ini = TRUE;
syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path);
if (Options.Count[OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE]) {
syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path);
}
}
/* SynVerilog needs the input from spice modeling */

3
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -211,7 +211,8 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path <path_to_generate_reports>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini <ini_file_path>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_simulation_ini_file <ini_file_path>\n");
/* Xifan Tang: Bitstream generator */
vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n");

41
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp
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@ -2,8 +2,8 @@
* This function includes the writer for generating exchangeable
* information, in order to interface different simulators
********************************************************************/
#include <math.h>
#include <time.h>
#include <cmath>
#include <ctime>
#include <map>
#define MINI_CASE_SENSITIVE
#include "ini.h"
@ -18,6 +18,11 @@
#include "verilog_global.h"
#include "simulation_info_writer.h"
/*********************************************************************
* Local Variable
********************************************************************/
constexpr char* DEFAULT_SIMULATION_INI_FILE_NAME = "simulation_deck_info.ini";
/*********************************************************************
* Top-level function to write an ini file which contains exchangeable
* information, in order to interface different Verilog simulators
@ -30,6 +35,22 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
const int& num_operating_clock_cycles,
const float& prog_clock_freq,
const float& op_clock_freq) {
/* Start time count */
clock_t t_start = clock();
/* Use default name if user does not provide one */
std::string ini_fname;
if (true == simulation_ini_filename.empty()) {
ini_fname = parent_dir + std::string(DEFAULT_SIMULATION_INI_FILE_NAME);
} else {
ini_fname = simulation_ini_filename;
}
vpr_printf(TIO_MESSAGE_INFO,
"Writing exchangeable file containing simulation information: %s...",
ini_fname.c_str());
mINI::INIStructure ini;
// std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
@ -50,14 +71,14 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v");
/* Use default name if user does not provide one */
std::string ini_fname;
if (true == simulation_ini_filename.empty()) {
ini_fname = parent_dir + std::string("SimulationDeckInfo.ini");
} else {
ini_fname = simulation_ini_filename;
}
mINI::INIFile file(ini_fname);
file.generate(ini, true);
/* End time count */
clock_t t_end = clock();
float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
vpr_printf(TIO_MESSAGE_INFO,
"took %g seconds\n",
run_time_sec);
}

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -438,7 +438,11 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) {
/* Print exchangeable files which contains simulation settings */
print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path),
std::string simulation_ini_file_name;
if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path) {
simulation_ini_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path);
}
print_verilog_simulation_info(simulation_ini_file_name,
std::string(format_dir_path(chomped_parent_dir)),
std::string(chomped_circuit_name),
std::string(src_dir_path),