refactoring analysis SDC generation
This commit is contained in:
tangxifan
parent
bcd8237263
commit
1f368abfbe
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@ -0,0 +1,260 @@
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/********************************************************************
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* This file includes functions that are used to output a SDC file
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* that constrain a FPGA fabric (P&Red netlist) using a benchmark
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*******************************************************************/
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#include <ctime>
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#include <fstream>
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#include <iomanip>
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#include "vtr_assert.h"
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#include "device_port.h"
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#include "util.h"
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#include "mux_utils.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_benchmark_utils.h"
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#include "sdc_writer_naming.h"
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#include "sdc_writer_utils.h"
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#include "analysis_sdc_writer.h"
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/********************************************************************
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* Generate SDC constaints for inputs and outputs
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* We consider the top module in formal verification purpose here
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* which is easier
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*******************************************************************/
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static
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void print_analysis_sdc_io_delays(std::fstream& fp,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitPortId>& global_ports,
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const float& critical_path_delay) {
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/* Validate the file stream */
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check_file_handler(fp);
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Create clock " << std::endl;
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fp << "##################################################" << std::endl;
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/* Get clock port from the global port */
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std::vector<BasicPort> operating_clock_ports;
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for (const CircuitPortId& clock_port : global_ports) {
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if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
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continue;
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}
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/* We only constrain operating clock here! */
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if (true == circuit_lib.port_is_prog(clock_port)) {
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continue;
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}
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/* Update the operating port list */
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operating_clock_ports.push_back(BasicPort(circuit_lib.port_prefix(clock_port), circuit_lib.port_size(clock_port)));
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}
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for (const BasicPort& operating_clock_port : operating_clock_ports) {
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/* Reach here, it means a clock port and we need print constraints */
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fp << "create_clock ";
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fp << generate_sdc_port(operating_clock_port);
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fp << " -period " << std::setprecision(10) << critical_path_delay;
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fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / 2 << "}";
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fp << std::endl;
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/* There should be only one operating clock!
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* TODO: this should be changed when developing multi-clock support!!!
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*/
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VTR_ASSERT(1 == operating_clock_ports.size());
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/* In this function, we support only 1 type of I/Os */
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VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
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BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
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/* Keep tracking which I/Os have been used */
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std::vector<bool> io_used(module_io_port.get_width(), false);
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Create input and output delays for used I/Os " << std::endl;
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fp << "##################################################" << std::endl;
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for (const t_logical_block& io_lb : L_logical_blocks) {
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/* We only care I/O logical blocks !*/
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if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) {
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continue;
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}
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/* clock net or constant generator should be disabled in timing analysis */
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if (TRUE == io_lb.is_clock) {
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continue;
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}
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/* Find the index of the mapped GPIO in top-level FPGA fabric */
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size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks);
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/* Ensure that IO index is in range */
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BasicPort module_mapped_io_port = module_io_port;
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/* Set the port pin index */
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VTR_ASSERT(io_index < module_mapped_io_port.get_width());
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module_mapped_io_port.set_width(io_index, io_index);
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/* For input I/O, we set an input delay constraint correlated to the operating clock
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* For output I/O, we set an output delay constraint correlated to the operating clock
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*/
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if (VPACK_INPAD == io_lb.type) {
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print_sdc_set_port_input_delay(fp, module_mapped_io_port,
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operating_clock_ports[0], critical_path_delay);
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} else {
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VTR_ASSERT(VPACK_OUTPAD == io_lb.type);
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print_sdc_set_port_output_delay(fp, module_mapped_io_port,
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operating_clock_ports[0], critical_path_delay);
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}
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/* Mark this I/O has been used/wired */
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io_used[io_index] = true;
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}
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Disable timing for unused I/Os " << std::endl;
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fp << "##################################################" << std::endl;
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/* Wire the unused iopads to a constant */
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for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
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/* Bypass used iopads */
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if (true == io_used[io_index]) {
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continue;
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}
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/* Wire to a contant */
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BasicPort module_unused_io_port = module_io_port;
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/* Set the port pin index */
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module_unused_io_port.set_width(io_index, io_index);
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print_sdc_disable_port_timing(fp, module_unused_io_port);
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}
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/********************************************************************
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* Top-level function outputs a SDC file
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* that constrain a FPGA fabric (P&Red netlist) using a benchmark
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*******************************************************************/
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void print_analysis_sdc(const std::string& sdc_dir,
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const float& critical_path_delay,
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const DeviceRRGSB& L_device_rr_gsb,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitPortId>& global_ports,
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const bool& compact_routing_hierarchy) {
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/* Create the file name for Verilog netlist */
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std::string sdc_fname(sdc_dir + std::string(SDC_ANALYSIS_FILE_NAME));
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating SDC for Timing/Power analysis on the mapped FPGA: %s ...",
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sdc_fname.c_str());
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/* Start time count */
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clock_t t_start = clock();
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/* Create the file stream */
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std::fstream fp;
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fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
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/* Validate file stream */
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check_file_handler(fp);
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/* Generate the descriptions*/
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print_sdc_file_header(fp, std::string("Constrain for Timing/Power analysis on the mapped FPGA"));
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/* Find the top_module */
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ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Create clock and set I/O ports with input/output delays */
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print_analysis_sdc_io_delays(fp,
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L_logical_blocks, device_size, L_grids, L_blocks,
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module_manager, top_module,
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circuit_lib, global_ports,
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critical_path_delay);
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/* TODO: Disable the timing for global ports */
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/*
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verilog_generate_sdc_disable_global_ports(fp);
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*/
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/* TODO: Disable the timing for configuration cells */
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/*
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verilog_generate_sdc_disable_sram_orgz(fp, cur_sram_orgz_info);
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*/
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/* TODO: Disable timing for un-used resources */
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/* Apply to Routing Channels */
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/*
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if (TRUE == compact_routing_hierarchy) {
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verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny);
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} else {
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verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny,
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LL_num_rr_nodes, LL_rr_node,
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LL_rr_node_indices);
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}
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*/
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/* TODO: Apply to Connection blocks */
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/*
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if (TRUE == compact_routing_hierarchy) {
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verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny, LL_device_rr_gsb);
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verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny, LL_device_rr_gsb);
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} else {
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verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny);
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verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny);
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}
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*/
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/* TODO: Apply to Switch blocks */
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/*
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if (TRUE == compact_routing_hierarchy) {
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verilog_generate_sdc_disable_unused_sbs(fp);
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verilog_generate_sdc_disable_unused_sbs_muxs(fp);
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} else {
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verilog_generate_sdc_disable_unused_sbs(fp, LL_nx, LL_ny);
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verilog_generate_sdc_disable_unused_sbs_muxs(fp, LL_nx, LL_ny);
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}
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*/
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/* TODO: Apply to Grids */
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/*
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verilog_generate_sdc_disable_unused_grids(fp, LL_nx, LL_ny, LL_grid, LL_block);
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verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block);
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*/
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/* Close file handler */
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fp.close();
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/* End time count */
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clock_t t_end = clock();
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float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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vpr_printf(TIO_MESSAGE_INFO,
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"took %g seconds\n",
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run_time_sec);
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}
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@ -0,0 +1,22 @@
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#ifndef ANALYSIS_SDC_WRITER_H
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#define ANALYSIS_SDC_WRITER_H
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#include <string>
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#include "vpr_types.h"
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#include "rr_blocks.h"
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#include "module_manager.h"
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#include "bitstream_manager.h"
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void print_analysis_sdc(const std::string& sdc_dir,
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const float& critical_path_delay,
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const DeviceRRGSB& L_device_rr_gsb,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitPortId>& global_ports,
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const bool& compact_routing_hierarchy);
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#endif
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@ -3,6 +3,7 @@
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*******************************************************************/
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#include <ctime>
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#include "pnr_sdc_writer.h"
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#include "analysis_sdc_writer.h"
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#include "sdc_api.h"
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@ -14,6 +15,10 @@ void fpga_sdc_generator(const SdcOption& sdc_options,
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const std::vector<std::vector<t_grid_tile>>& grids,
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const std::vector<t_switch_inf>& switches,
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const DeviceRRGSB& L_device_rr_gsb,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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@ -33,6 +38,16 @@ void fpga_sdc_generator(const SdcOption& sdc_options,
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compact_routing_hierarchy);
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}
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if (true == sdc_options.generate_sdc_analysis()) {
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print_analysis_sdc(sdc_options.sdc_dir(),
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critical_path_delay,
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L_device_rr_gsb,
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L_logical_blocks, device_size, L_grids, L_blocks,
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module_manager,
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circuit_lib, global_ports,
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compact_routing_hierarchy);
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}
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/* End time count */
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clock_t t_end = clock();
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@ -12,6 +12,10 @@ void fpga_sdc_generator(const SdcOption& sdc_options,
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const std::vector<std::vector<t_grid_tile>>& grids,
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const std::vector<t_switch_inf>& switches,
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const DeviceRRGSB& L_device_rr_gsb,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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@ -10,4 +10,6 @@ constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer
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constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc";
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constexpr char* SDC_CB_FILE_NAME = "cb.sdc";
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constexpr char* SDC_ANALYSIS_FILE_NAME = "fpga_top_analysis.sdc";
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#endif
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@ -99,3 +99,74 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
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tmax);
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}
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/********************************************************************
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* Disable timing for a port
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*******************************************************************/
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void print_sdc_disable_port_timing(std::fstream& fp,
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const BasicPort& port) {
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/* Validate file stream */
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check_file_handler(fp);
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fp << "set_disable_timing ";
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fp << generate_sdc_port(port);
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fp << std::endl;
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}
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/********************************************************************
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* Set the input delay for a port in SDC format
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* Note that the input delay will be bounded by a clock port
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*******************************************************************/
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void print_sdc_set_port_input_delay(std::fstream& fp,
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const BasicPort& port,
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const BasicPort& clock_port,
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const float& delay) {
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/* Validate file stream */
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check_file_handler(fp);
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fp << "set_input_delay ";
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fp << "-clock ";
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fp << generate_sdc_port(clock_port);
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fp << " -max ";
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fp << std::setprecision(10) << delay;
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fp << " ";
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fp << generate_sdc_port(port);
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fp << std::endl;
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}
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/********************************************************************
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* Set the output delay for a port in SDC format
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* Note that the output delay will be bounded by a clock port
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*******************************************************************/
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void print_sdc_set_port_output_delay(std::fstream& fp,
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const BasicPort& port,
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const BasicPort& clock_port,
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const float& delay) {
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/* Validate file stream */
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check_file_handler(fp);
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fp << "set_output_delay ";
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fp << "-clock ";
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fp << generate_sdc_port(clock_port);
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fp << " -max ";
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fp << std::setprecision(10) << delay;
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fp << " ";
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fp << generate_sdc_port(port);
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fp << std::endl;
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}
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@ -26,4 +26,17 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
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const ModulePortId& module_output_port_id,
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const float& tmax);
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void print_sdc_disable_port_timing(std::fstream& fp,
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const BasicPort& port);
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void print_sdc_set_port_input_delay(std::fstream& fp,
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const BasicPort& port,
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const BasicPort& clock_port,
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const float& delay);
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void print_sdc_set_port_output_delay(std::fstream& fp,
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const BasicPort& port,
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const BasicPort& clock_port,
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const float& delay);
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#endif
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@ -160,6 +160,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
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fpga_sdc_generator(sdc_options,
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Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9,
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grids, rr_switches, device_rr_gsb,
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L_logical_blocks, device_size, grids, L_blocks,
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module_manager, mux_lib,
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Arch.spice->circuit_lib, global_ports,
|
||||
TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
|
||||
|
|
|
|||
Loading…
Reference in New Issue