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7778 Commits

Author SHA1 Message Date
Pepijn de Vos c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos 293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos 5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos 8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos 83fbfe0964 Add some tests 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
 2019-10-21 16:25:15 +02:00
Pepijn de Vos 03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Pepijn de Vos 8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos 69fb3b8db2 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-10-21 10:51:34 +02:00
David Shah fa989e59e5 ecp5: Pass -nomfs to abc9 
Fixes #1459

Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:30:41 +01:00
Miodrag Milanović f2aa2d1bb4
Merge pull request #1457 from xobs/python-binary-name 
Makefile: don't assume python is called `python3`
 2019-10-19 08:58:02 +02:00
Sean Cross 82f60ba938 Makefile: don't assume python is called `python3` 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Miodrag Milanović e8ef3fcdfc
Merge pull request #1454 from YosysHQ/mmicko/common_tests 
Share common tests
 2019-10-18 14:29:44 +02:00
Miodrag Milanovic 190b40341a fixed error 2019-10-18 13:15:36 +02:00
Miodrag Milanovic 9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
Miodrag Milanovic 12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic 477702b8c9 Remove not needed tests 2019-10-18 12:20:35 +02:00
Miodrag Milanovic 5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic 56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Miodrag Milanovic 3c41599ee1 Add async2sync 2019-10-18 11:00:27 +02:00
Miodrag Milanović 0568920d79
Merge pull request #1435 from YosysHQ/mmicko/efinix 
Add tests for Efinix architecture (contd)
 2019-10-18 10:54:35 +02:00
Miodrag Milanović b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
Miodrag Milanović ab4899a2d0
Merge pull request #1434 from YosysHQ/mmicko/anlogic 
Add tests for Anlogic architecture (contd)
 2019-10-18 10:54:04 +02:00
Miodrag Milanović 66fca65b58
Merge branch 'master' into mmicko/anlogic 2019-10-18 10:53:56 +02:00
Miodrag Milanović 5ffb0053ec
Merge pull request #1421 from YosysHQ/eddie/pr1352 
Add tests for ECP5 architecture (contd)
 2019-10-18 10:53:34 +02:00
Miodrag Milanović 0b0b0cc0d9
Merge branch 'master' into eddie/pr1352 2019-10-18 10:52:50 +02:00
Miodrag Milanović e0a67fce12
Merge pull request #1420 from YosysHQ/eddie/pr1363 
Add tests for Xilinx architecture (contd)
 2019-10-18 10:51:32 +02:00
Miodrag Milanovic b659082e4a hierarchy - proc reorder 2019-10-18 09:13:06 +02:00
Miodrag Milanovic 46af9a0ff7 hierarchy - proc reorder 2019-10-18 09:06:43 +02:00
Miodrag Milanovic 0d60902fd9 hierarchy - proc reorder 2019-10-18 09:04:02 +02:00
Miodrag Milanovic e6ad714d20 hierarchy - proc reorder 2019-10-18 08:06:57 +02:00
Miodrag Milanovic 980df499ab Make equivalence work with latest master 2019-10-17 17:24:53 +02:00
Miodrag Milanovic b2f0d75807 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 1a399c6456 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic a198bcdd4f split muxes synth per type 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 36af102801 Test dffs separetely 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic 53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung 3b44084320 Add -assert 2019-10-17 17:10:42 +02:00
Eddie Hung 8422ad3e3a Use built-in async2sync call as per #1417 2019-10-17 17:10:42 +02:00
Eddie Hung 5b7bc3ab85 Update mul test to DSP48E1 2019-10-17 17:10:02 +02:00
Eddie Hung 08bd1816e3 Update area for div_mod 2019-10-17 17:10:02 +02:00
Eddie Hung a12801843b Add comment for lack of tristate logic pointing to #1225 2019-10-17 17:10:02 +02:00
Eddie Hung eded90b6b4 Move $x to end as 7f0eec8 2019-10-17 17:10:02 +02:00