mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1421 from YosysHQ/eddie/pr1352
Add tests for ECP5 architecture (contd)
This commit is contained in:
Miodrag Milanović
GitHub
commit
5ffb0053ec
1
Makefile
1
Makefile
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@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/arch && bash run-test.sh
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+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
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+cd tests/rpc && bash run-test.sh
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+cd tests/ecp5 && bash run-test.sh $(SEEDOPT)
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+cd tests/xilinx && bash run-test.sh $(SEEDOPT)
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@echo ""
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@echo " Passed \"make test\"."
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@ -0,0 +1,2 @@
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*.log
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/run-test.mk
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@ -0,0 +1,13 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x + y;
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assign B = x - y;
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endmodule
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@ -0,0 +1,9 @@
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read_verilog add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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@ -0,0 +1,47 @@
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module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffs
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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@ -0,0 +1,40 @@
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read_verilog adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-count 1 t:LUT4
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select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
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@ -0,0 +1,17 @@
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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@ -0,0 +1,10 @@
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read_verilog counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 4 t:CCU2C
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select -assert-count 8 t:TRELLIS_FF
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select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D
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@ -0,0 +1,15 @@
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module dff
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe
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( input d, clk, en, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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@ -0,0 +1,19 @@
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read_verilog dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:TRELLIS_FF
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select -assert-none t:TRELLIS_FF %% t:* %D
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@ -0,0 +1,23 @@
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/*
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Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
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*/
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module top (din, write_en, waddr, wclk, raddr, rclk, dout);
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parameter addr_width = 8;
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parameter data_width = 8;
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input [addr_width-1:0] waddr, raddr;
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input [data_width-1:0] din;
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input write_en, wclk, rclk;
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output [data_width-1:0] dout;
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reg [data_width-1:0] dout;
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reg [data_width-1:0] mem [(1<<addr_width)-1:0]
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/* synthesis syn_ramstyle = "no_rw_check" */ ;
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always @(posedge wclk) // Write memory.
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begin
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if (write_en)
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mem[waddr] <= din; // Using write address bus.
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end
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always @(posedge rclk) // Read memory.
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begin
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dout <= mem[raddr]; // Using read address bus.
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end
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endmodule
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@ -0,0 +1,18 @@
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read_verilog dpram.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#Blocked by issue #1358 (Missing ECP5 simulation models)
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#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 1 t:DP16KD
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select -assert-none t:DP16KD %% t:* %D
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@ -0,0 +1,55 @@
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module fsm (
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clock,
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reset,
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req_0,
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req_1,
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gnt_0,
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gnt_1
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);
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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@ -0,0 +1,12 @@
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read_verilog fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:L6MUX21
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select -assert-count 13 t:LUT4
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select -assert-count 5 t:PFUMX
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select -assert-count 5 t:TRELLIS_FF
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select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
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@ -0,0 +1,24 @@
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module latchp
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( input d, clk, en, output reg q );
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always @*
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if ( en )
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q <= d;
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endmodule
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module latchn
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( input d, clk, en, output reg q );
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always @*
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if ( !en )
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q <= d;
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endmodule
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module latchsr
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( input d, clk, en, clr, pre, output reg q );
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always @*
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else if ( en )
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q <= d;
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endmodule
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@ -0,0 +1,35 @@
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read_verilog latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 1 t:PFUMX
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select -assert-none t:LUT4 t:PFUMX %% t:* %D
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|
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@ -0,0 +1,18 @@
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module top
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(
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input [0:7] in,
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output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
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);
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assign B1 = in[0] & in[1];
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assign B2 = in[0] | in[1];
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assign B3 = in[0] ~& in[1];
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assign B4 = in[0] ~| in[1];
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assign B5 = in[0] ^ in[1];
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assign B6 = in[0] ~^ in[1];
|
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assign B7 = ~in[0];
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assign B8 = in[0];
|
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assign B9 = in[0:1] && in [2:3];
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assign B10 = in[0:1] || in [2:3];
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endmodule
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|
|
@ -0,0 +1,8 @@
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read_verilog logic.v
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hierarchy -top top
|
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proc
|
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 9 t:LUT4
|
||||
select -assert-none t:LUT4 %% t:* %D
|
||||
|
|
@ -0,0 +1,25 @@
|
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/*
|
||||
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
|
||||
*/
|
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module top(clk,a,b,c,set);
|
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parameter A_WIDTH = 4;
|
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parameter B_WIDTH = 3;
|
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input set;
|
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input clk;
|
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input signed [(A_WIDTH - 1):0] a;
|
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input signed [(B_WIDTH - 1):0] b;
|
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output signed [(A_WIDTH + B_WIDTH - 1):0] c;
|
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reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
|
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assign c = reg_tmp_c;
|
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always @(posedge clk)
|
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begin
|
||||
if(set)
|
||||
begin
|
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reg_tmp_c <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reg_tmp_c <= a * b + c;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog macc.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
# Blocked by issue #1358 (Missing ECP5 simulation models)
|
||||
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT18X18D
|
||||
select -assert-count 4 t:CCU2C
|
||||
select -assert-count 7 t:TRELLIS_FF
|
||||
|
||||
select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module top
|
||||
(
|
||||
input [7:0] data_a,
|
||||
input [6:1] addr_a,
|
||||
input we_a, clk,
|
||||
output reg [7:0] q_a
|
||||
);
|
||||
// Declare the RAM variable
|
||||
reg [7:0] ram[63:0];
|
||||
|
||||
// Port A
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (we_a)
|
||||
begin
|
||||
ram[addr_a] <= data_a;
|
||||
q_a <= data_a;
|
||||
end
|
||||
q_a <= ram[addr_a];
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
read_verilog memory.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd top
|
||||
select -assert-count 24 t:L6MUX21
|
||||
select -assert-count 71 t:LUT4
|
||||
select -assert-count 32 t:PFUMX
|
||||
select -assert-count 8 t:TRELLIS_DPR16X4
|
||||
select -assert-count 35 t:TRELLIS_FF
|
||||
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
module top
|
||||
(
|
||||
input [5:0] x,
|
||||
input [5:0] y,
|
||||
|
||||
output [11:0] A,
|
||||
);
|
||||
|
||||
assign A = x * y;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
read_verilog mul.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
# Blocked by issue #1358 (Missing ECP5 simulation models)
|
||||
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MULT18X18D
|
||||
select -assert-none t:MULT18X18D %% t:* %D
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
read_verilog mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-none t:LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:L6MUX21
|
||||
select -assert-count 4 t:LUT4
|
||||
select -assert-count 2 t:PFUMX
|
||||
|
||||
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:L6MUX21
|
||||
select -assert-count 7 t:LUT4
|
||||
select -assert-count 2 t:PFUMX
|
||||
|
||||
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:L6MUX21
|
||||
select -assert-count 26 t:LUT4
|
||||
select -assert-count 12 t:PFUMX
|
||||
|
||||
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
|
||||
*/
|
||||
module top(data, addr);
|
||||
output [3:0] data;
|
||||
input [4:0] addr;
|
||||
always @(addr) begin
|
||||
case (addr)
|
||||
0 : data = 'h4;
|
||||
1 : data = 'h9;
|
||||
2 : data = 'h1;
|
||||
15 : data = 'h8;
|
||||
16 : data = 'h1;
|
||||
17 : data = 'h0;
|
||||
default : data = 'h0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
read_verilog rom.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 6 t:LUT4
|
||||
select -assert-count 3 t:PFUMX
|
||||
select -assert-none t:LUT4 t:PFUMX %% t:* %D
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#!/usr/bin/env bash
|
||||
set -e
|
||||
{
|
||||
echo "all::"
|
||||
for x in *.ys; do
|
||||
echo "all:: run-$x"
|
||||
echo "run-$x:"
|
||||
echo " @echo 'Running $x..'"
|
||||
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
|
||||
done
|
||||
for s in *.sh; do
|
||||
if [ "$s" != "run-test.sh" ]; then
|
||||
echo "all:: run-$s"
|
||||
echo "run-$s:"
|
||||
echo " @echo 'Running $s..'"
|
||||
echo " @bash $s"
|
||||
fi
|
||||
done
|
||||
} > run-test.mk
|
||||
exec ${MAKE:-make} -f run-test.mk
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
out <= out >> 1;
|
||||
out[7] <= in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
read_verilog shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 8 t:TRELLIS_FF
|
||||
select -assert-none t:TRELLIS_FF %% t:* %D
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
module tristate (en, i, o);
|
||||
input en;
|
||||
input i;
|
||||
output o;
|
||||
|
||||
assign o = en ? i : 1'bz;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
read_verilog tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
Loading…
Reference in New Issue