mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1435 from YosysHQ/mmicko/efinix
Add tests for Efinix architecture (contd)
This commit is contained in:
Miodrag Milanović
GitHub
commit
0568920d79
1
Makefile
1
Makefile
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@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/arch && bash run-test.sh
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+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
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+cd tests/rpc && bash run-test.sh
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+cd tests/efinix && bash run-test.sh $(SEEDOPT)
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+cd tests/anlogic && bash run-test.sh $(SEEDOPT)
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+cd tests/ecp5 && bash run-test.sh $(SEEDOPT)
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+cd tests/xilinx && bash run-test.sh $(SEEDOPT)
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@ -17,6 +17,18 @@ module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE
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module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
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module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = !E ? D : Q;
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endmodule
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module \$_DLATCH_P_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = E ? D : Q;
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endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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parameter WIDTH = 0;
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@ -59,7 +59,9 @@ module EFX_FF(
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assign ce = CE_POLARITY ? CE : ~CE;
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assign sr = SR_POLARITY ? SR : ~SR;
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assign d = D_POLARITY ? D : ~D;
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initial Q = 1'b0;
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generate
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if (SR_SYNC == 1)
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begin
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@ -0,0 +1,3 @@
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/*.log
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/*.out
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/run-test.mk
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@ -0,0 +1,13 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x + y;
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assign B = x - y;
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endmodule
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@ -0,0 +1,10 @@
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read_verilog add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:EFX_ADD
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select -assert-count 4 t:EFX_LUT4
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select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
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@ -0,0 +1,47 @@
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module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffs
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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@ -0,0 +1,50 @@
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read_verilog adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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@ -0,0 +1,17 @@
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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@ -0,0 +1,12 @@
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read_verilog counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 8 t:EFX_FF
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select -assert-count 9 t:EFX_ADD
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select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D
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@ -0,0 +1,15 @@
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module dff
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe
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( input d, clk, en, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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@ -0,0 +1,24 @@
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read_verilog dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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@ -0,0 +1,55 @@
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module fsm (
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clock,
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reset,
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req_0,
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req_1,
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gnt_0,
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gnt_1
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);
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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@ -0,0 +1,14 @@
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read_verilog fsm.v
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hierarchy -top fsm
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proc
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flatten
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#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
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#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 6 t:EFX_FF
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select -assert-count 15 t:EFX_LUT4
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select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
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@ -0,0 +1,24 @@
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module latchp
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( input d, clk, en, output reg q );
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always @*
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if ( en )
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q <= d;
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endmodule
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module latchn
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( input d, clk, en, output reg q );
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always @*
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if ( !en )
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q <= d;
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endmodule
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module latchsr
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( input d, clk, en, clr, pre, output reg q );
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always @*
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else if ( en )
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q <= d;
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endmodule
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@ -0,0 +1,33 @@
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read_verilog latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_efinix
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_LUT4 %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_efinix
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_LUT4 %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
|
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synth_efinix
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 2 t:EFX_LUT4
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select -assert-none t:EFX_LUT4 %% t:* %D
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|
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@ -0,0 +1,18 @@
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module top
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(
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input [0:7] in,
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output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
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);
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assign B1 = in[0] & in[1];
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assign B2 = in[0] | in[1];
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assign B3 = in[0] ~& in[1];
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assign B4 = in[0] ~| in[1];
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assign B5 = in[0] ^ in[1];
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assign B6 = in[0] ~^ in[1];
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assign B7 = ~in[0];
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assign B8 = in[0];
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assign B9 = in[0:1] && in [2:3];
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assign B10 = in[0:1] || in [2:3];
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endmodule
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|
|
@ -0,0 +1,9 @@
|
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read_verilog logic.v
|
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hierarchy -top top
|
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proc
|
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
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cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 9 t:EFX_LUT4
|
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select -assert-none t:EFX_LUT4 %% t:* %D
|
||||
|
|
@ -0,0 +1,21 @@
|
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module top
|
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(
|
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input [7:0] data_a,
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input [8:1] addr_a,
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input we_a, clk,
|
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output reg [7:0] q_a
|
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);
|
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// Declare the RAM variable
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reg [7:0] ram[63:0];
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|
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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begin
|
||||
ram[addr_a] <= data_a;
|
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q_a <= data_a;
|
||||
end
|
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q_a <= ram[addr_a];
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
read_verilog memory.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
|
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memory
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opt -full
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||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
#ERROR: Called with -verify and proof did fail!
|
||||
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd top
|
||||
select -assert-count 1 t:EFX_GBUFCE
|
||||
select -assert-count 1 t:EFX_RAM_5K
|
||||
select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
read_verilog mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:EFX_LUT4
|
||||
|
||||
select -assert-none t:EFX_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:EFX_LUT4
|
||||
|
||||
select -assert-none t:EFX_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 5 t:EFX_LUT4
|
||||
|
||||
select -assert-none t:EFX_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 12 t:EFX_LUT4
|
||||
|
||||
select -assert-none t:EFX_LUT4 %% t:* %D
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#!/usr/bin/env bash
|
||||
set -e
|
||||
{
|
||||
echo "all::"
|
||||
for x in *.ys; do
|
||||
echo "all:: run-$x"
|
||||
echo "run-$x:"
|
||||
echo " @echo 'Running $x..'"
|
||||
echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
|
||||
done
|
||||
for s in *.sh; do
|
||||
if [ "$s" != "run-test.sh" ]; then
|
||||
echo "all:: run-$s"
|
||||
echo "run-$s:"
|
||||
echo " @echo 'Running $s..'"
|
||||
echo " @bash $s"
|
||||
fi
|
||||
done
|
||||
} > run-test.mk
|
||||
exec ${MAKE:-make} -f run-test.mk
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
out <= out << 1;
|
||||
out[7] <= in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
read_verilog shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:EFX_GBUFCE
|
||||
select -assert-count 8 t:EFX_FF
|
||||
select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
module tristate (en, i, o);
|
||||
input en;
|
||||
input i;
|
||||
output reg o;
|
||||
|
||||
always @(en or i)
|
||||
o <= (en)? i : 1'bZ;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
read_verilog tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
tribuf
|
||||
flatten
|
||||
synth
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
#Internal cell type used. Need support it.
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
Loading…
Reference in New Issue