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324 Commits

Author SHA1 Message Date
Miodrag Milanovic 436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic 1937091f62 iopad no op for compatibility with old scripts 2019-12-21 13:21:45 +01:00
Miodrag Milanovic 2fcf683af4 Make iopad option default for all xilinx flows 2019-12-21 11:56:41 +01:00
Eddie Hung 10e82e103f
Revert "Optimise write_xaiger" 2019-12-20 12:05:45 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup 
Optimise write_xaiger
 2019-12-19 12:24:03 -05:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung dd7d2d8db6 Duplicate tribuf call, credit to @mwkmwkmwk 2019-12-13 08:51:05 -08:00
Eddie Hung 3bd623bb05 synth_xilinx: error out if tristate without '-iopad' 2019-12-12 14:33:33 -08:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung 02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Marcin Kościelnicki fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Eddie Hung 0add5965c7 techmap abc_unmap.v before xilinx_srl -fixed 2019-12-03 14:27:45 -08:00
Eddie Hung b1ab7c16c4 clkpart -unpart into 'finalize' 2019-11-28 12:59:43 -08:00
Eddie Hung df8dc6d1fb ean call after abc{,9} 2019-11-27 09:10:34 -08:00
Eddie Hung 739f530906 Move 'clean' from map_luts to finalize 2019-11-26 14:51:39 -08:00
Eddie Hung eb11c06a69 For abc9, run clkpart before ff_map and after abc9 2019-11-23 10:18:22 -08:00
Eddie Hung 09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Marcin Kościelnicki c4bd318e76 synth_xilinx: Merge blackbox primitive libraries. 
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.

Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included.  Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.

Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).

Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
 2019-11-06 15:11:27 +01:00
David Shah 3506eaf290 xilinx: Add URAM288 mapping for xcup 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:44 +01:00
David Shah 6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Marcin Kościelnicki 7b350cacd4 xilinx: Support multiplier mapping for all families. 
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
 2019-10-22 18:06:57 +02:00
N. Engelhardt 3b405d985e Call memory_dff before DSP mapping to reserve registers (fixes #1447) 2019-10-17 21:33:54 +02:00
Eddie Hung 304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung 9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 
Rename abc_* names/attributes to more precisely be abc9_*
 2019-10-08 10:53:38 -07:00
Eddie Hung 1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 5c1271c51c Move "(skip if -nodsp)" message to label 2019-09-10 15:26:56 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung c460d10e60 Remove wreduce call 2019-09-10 14:17:35 -07:00
Eddie Hung f3a55d3f06 Add comment for why opt_expr is necessary 2019-09-10 14:11:56 -07:00
Eddie Hung 8514e7c32e Revert "Remove "opt_expr -fine" call" 
This reverts commit bfda921d03.
 2019-09-10 14:09:21 -07:00
Eddie Hung d3fb308181 Rename label to map_dsp 2019-09-10 13:18:10 -07:00
Eddie Hung bfda921d03 Remove "opt_expr -fine" call 2019-09-10 13:17:47 -07:00
Marcin Kościelnicki fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
Eddie Hung 1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung c7af71ecde Use semicolon 2019-08-21 11:47:17 -07:00
Eddie Hung 5d0f6cbd54 techmap before read 2019-08-21 11:47:06 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung 30a379b5b6 Cleanup techmap in map_luts 2019-08-20 17:59:31 -07:00
Eddie Hung 3b52d6e29c Move `techmap abc_map.v` into map_luts 2019-08-20 17:55:12 -07:00
Eddie Hung 8f666ebac1 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 17:36:14 -07:00
Eddie Hung 5eda5fc7eb Remove -icells 2019-08-20 12:41:11 -07:00
Eddie Hung be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Eddie Hung 24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung 261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Eddie Hung 0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung 162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00