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308 Commits

Author SHA1 Message Date
Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Udi Finkelstein 106af19b69 Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
Johnny Sorocil 0295213bec autotest.sh: Change from /bin/bash to /usr/bin/env bash 
This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
 2018-05-06 15:26:23 +02:00
Clifford Wolf 5e49ee5c2d Fix tests/simple/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf 25e33d7ab8 Major redesign of Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-27 20:33:15 +01:00
Clifford Wolf 6d12c83d36 Add support for SVA throughout via Verific 2018-02-21 13:09:47 +01:00
Clifford Wolf 5c6247dfa6 Add support for SVA sequence concatenation ranges via verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 16:35:06 +01:00
Clifford Wolf 9d963cd29c Add support for SVA until statements via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 14:57:52 +01:00
Clifford Wolf bc8ab3ab44 Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF 2018-02-15 15:26:37 +01:00
Clifford Wolf baddb017fe Remove PSL example from tests/sva/ 2017-10-20 13:16:24 +02:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein 6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Udi Finkelstein 2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein 17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein 64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf 4cf890dac1 Add simple VHDL+PSL example 2017-07-28 17:39:43 +02:00
Clifford Wolf c1cfca8f54 Improve Verific SVA importer 2017-07-27 14:05:09 +02:00
Clifford Wolf 877ff1f75e Add counter.sv SVA test 2017-07-27 12:37:16 +02:00
Clifford Wolf b24f737759 Improve SVA tests, add Makefile and scripts 2017-07-27 11:42:05 +02:00
Clifford Wolf 84f15260b5 Add more SVA test cases for future Verific work 2017-07-22 16:35:46 +02:00
Clifford Wolf 024ba310ec Add some simple SVA test cases for future Verific work 2017-07-22 12:31:08 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf 080004b19a Fixed typo in tests/simple/arraycells.v 2017-01-04 12:39:01 +01:00
Clifford Wolf 5c96982522 Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
rodrigosiqueira b932e2355d Improved unit test structure 
Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>

* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
 2016-12-10 18:21:56 -02:00
rodrigosiqueira e0152319f5 Added required structure to implement unit tests 
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.

Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
 2016-12-04 11:34:27 -02:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf 1e3c2bff72 Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
Clifford Wolf 4a981a3bd8 Fixed "make test" for git head of iverilog 2016-10-11 12:12:32 +02:00
Clifford Wolf 6300c0b3c2 Merge branch 'master' of https://github.com/brouhaha/yosys 2016-09-23 13:42:08 +02:00
Eric Smith f4240cc8a4 Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
Clifford Wolf 0c697b9eac Added autotest.sh -I 2016-09-20 09:29:56 +02:00
Kaj Tuomi 2c031cd24f Fix for modules with big interfaces. 2016-09-13 13:13:27 +03:00
Clifford Wolf 450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf cdd0b85e47 Added another mem2reg test case 2016-08-21 13:45:46 +02:00
Clifford Wolf 82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf 88a67afa7d Added "test_autotb -seed" (and "autotest.sh -S") 2016-08-06 13:32:29 +02:00
Clifford Wolf 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
Clifford Wolf e420412043 Fixed autotest.sh handling of `timescale 2016-07-02 13:32:20 +02:00
Clifford Wolf 7a4ee5da74 Fixed init issue in mem2reg_test2 test case 2016-06-17 20:15:11 +02:00
Clifford Wolf 11f7b8a2a1 Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
Clifford Wolf 8e9e793126 Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
Clifford Wolf 1e227caf72 Improvements and fixes in autotest.sh script and test_autotb 2016-05-20 16:58:02 +02:00
Kaj Tuomi f6221ade95 Fix for Modelsim transcript line warp issue #164 2016-05-19 11:34:38 +03:00
Clifford Wolf 1761d08dd2 Bugfix and improvements in memory_share 2016-04-21 14:22:58 +02:00
Sergey Kvachonok e14055edf0 Optionally use ${CC} when compiling test utils. 
Default to gcc when not set.
 2016-03-25 10:35:42 +03:00
Clifford Wolf 0f94902125 Added tests/simple/graphtest.v 2015-11-30 11:41:12 +01:00
Clifford Wolf 7ae3d1b5a9 More bugfixes in handling of parameters in tasks and functions 2015-11-12 13:02:36 +01:00
Clifford Wolf 34f2b84fb6 Fixed handling of parameters and localparams in functions 2015-11-11 10:54:35 +01:00
Clifford Wolf ddf3e2dc65 Bugfix in memory_dff 2015-10-31 22:01:41 +01:00
Clifford Wolf ccdbf41be6 Improvements in wreduce 2015-10-31 13:39:30 +01:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf ad8efeb13f Fixed CRLF line endings 2015-08-13 09:35:00 +02:00
Clifford Wolf 08ad5409a2 Some ASCII encoding fixes (comments and docs) by Larry Doolittle 2015-08-13 09:30:20 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 8c79765de5 Progress in SMV back-end 2015-06-19 14:08:46 +02:00
Clifford Wolf 8a86162ae9 Progress in SMV back-end 2015-06-18 16:29:11 +02:00
Clifford Wolf 6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00
Clifford Wolf 83499dc1ba added vloghtb test_febe.sh 2015-05-17 19:54:00 +02:00
Clifford Wolf dae00e1d83 changed file() to open() in python scripts 2015-05-11 21:58:21 +02:00
Clifford Wolf 724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf 604c097f98 fix for python 2.6.6 2015-03-20 09:10:02 +01:00
Clifford Wolf e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 913c304fe6 Added $meminit test case 2015-02-14 11:26:20 +01:00
Clifford Wolf d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf e666611534 Bugfix in resource sharing test 2015-01-27 19:30:06 +01:00
Clifford Wolf 8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf 694cc01f1d improvements in muxtree/select_leaves test 2015-01-18 13:24:01 +01:00
Clifford Wolf f630868bc9 Improvements in opt_muxtree 2015-01-18 12:57:36 +01:00
Clifford Wolf dfa42e272c Tiny fix in vcdcd.pl 2015-01-13 12:59:29 +01:00
Clifford Wolf daae35319b Added memory_bram "shuffle_enable" feature 2015-01-04 13:14:30 +01:00
Clifford Wolf 45918b8315 Added "memory -bram" 2015-01-03 17:40:20 +01:00
Clifford Wolf a7fe87f888 Added memory_bram 'or_next_if_better' feature 2015-01-03 17:34:05 +01:00
Clifford Wolf fd2c224c04 memory_bram transp support 2015-01-03 12:41:46 +01:00
Clifford Wolf a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf 90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf 1dca7ae486 Fixes and improvements in bram test 2015-01-02 18:54:22 +01:00
Clifford Wolf 03b3c02540 Progress in bram testbench 2015-01-02 17:50:15 +01:00
Clifford Wolf bbf89c4dc6 Progress in memory_bram 2015-01-02 13:59:47 +01:00
Clifford Wolf 36c20f2ede Progress in memory_bram 2015-01-02 00:07:44 +01:00
Clifford Wolf 24ae156a74 Progress in bram testbench 2015-01-01 20:58:33 +01:00
Clifford Wolf 340e769667 Bram testbench (incomplete) 2015-01-01 17:01:17 +01:00
Clifford Wolf 1e0f6b5ddb Added "yosys -qq" to also quiet warning messages 2014-11-09 11:02:20 +01:00
Clifford Wolf f9c096eeda Added support for task and function args in parentheses 2014-10-27 13:21:57 +01:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf 76f8128123 Fixed autotest for non-basename arguments 2014-09-06 12:10:57 +02:00
Clifford Wolf 01ef34c147 Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
Clifford Wolf 88db09255b Added autotest -e (do not use -noexpr on write_verilog) 2014-08-30 18:34:07 +02:00