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7773 Commits

Author SHA1 Message Date
Eddie Hung 9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung 74ef8feeaf Fix xilinx_dsp for unsigned extensions 2019-10-04 16:46:15 -07:00
Eddie Hung 6bf7114bbd Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again 2019-10-04 16:45:36 -07:00
Eddie Hung 279fd22ddf Add Const::{begin,end,empty}() 2019-10-04 15:00:57 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung 4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Eddie Hung 84f978bdc2 Add -async2sync to help text as per @daveshah1 2019-10-04 10:17:46 -07:00
Miodrag Milanovic c0b14cfea7 Fixes for MSVC build 2019-10-04 16:29:46 +02:00
Miodrag Milanovic 44c3472b9f FF should be initialized to 0 2019-10-04 13:27:10 +02:00
Miodrag Milanovic c0fa6f3e1a Split mux tests per type 2019-10-04 13:05:16 +02:00
Miodrag Milanovic 1b80489486 Split latch check 2019-10-04 13:00:09 +02:00
Miodrag Milanovic 77d557d00b Add missing latch mapping 2019-10-04 12:58:11 +02:00
Miodrag Milanovic 2c3e140246 split rest od ff's 2019-10-04 12:51:45 +02:00
Miodrag Milanovic 3de7889d08 Separate check for ff's types 2019-10-04 12:48:27 +02:00
Miodrag Milanovic 286a272872 Cleaned tests 2019-10-04 12:42:06 +02:00
Miodrag Milanovic f94dc2c072 Remove not needed tests 2019-10-04 12:41:41 +02:00
Miodrag Milanovic ef417fb1b3 Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix 2019-10-04 12:20:49 +02:00
Miodrag Milanovic 03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic 3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic 91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic 1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Miodrag Milanovic b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Miodrag Milanovic 7785f23719 Check latches type one by one 2019-10-04 10:31:51 +02:00
Miodrag Milanovic 3358b2f185 Removed top module where not needed 2019-10-04 09:53:54 +02:00
Miodrag Milanovic 3c40c81030 Test muxes synth one by one 2019-10-04 08:52:54 +02:00
Miodrag Milanovic d6ef9b1a6b Cleaned verilog code from not used defines 2019-10-04 08:45:58 +02:00
Miodrag Milanovic abb5a3a44d Check for MULT18X18D, since that is working now 2019-10-04 08:44:10 +02:00
Miodrag Milanovic 9e8175fc75 Check flops one by one 2019-10-04 08:42:29 +02:00
Miodrag Milanovic d19f765a58 Removed alu and div_mod tests as agreed 2019-10-04 08:41:53 +02:00
Eddie Hung 045f344038 Use `sat -tempinduct` and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung a9efd2e81c Restore part of doc 2019-10-03 10:51:53 -07:00
Eddie Hung bd5889640b Disable equiv check for ice40 latches 2019-10-03 10:45:53 -07:00
Eddie Hung 7a6dec1cef Add new -async2sync option 2019-10-03 10:30:51 -07:00
Eddie Hung 5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Eddie Hung 8765ec3c27 Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys" 
This reverts commit a39505e329.
 2019-10-03 10:07:15 -07:00
Eddie Hung c6d15c9aad Revert "Update doc for equiv_opt" 
This reverts commit a274b7cc86.
 2019-10-03 10:07:03 -07:00
Clifford Wolf 2ed2e9c3e8 Change smtbmc "Warmup failed" status to "PREUNSAT" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:59:07 +02:00
Clifford Wolf 17cb916cc8 Update ABC to git rev 623b5e8 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:05:21 +02:00
Clifford Wolf be8efd7c7b Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 12:26:08 +02:00
Clifford Wolf 468b8a5178
Merge pull request #1419 from YosysHQ/eddie/lazy_derive 
module->derive() to be lazy and not touch ast if already derived
 2019-10-03 12:06:12 +02:00
Clifford Wolf 0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
Clifford Wolf afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped 
Add "check -mapped"
 2019-10-03 11:50:53 +02:00
Clifford Wolf 3e27b2846b Add "check -allow-tbuf" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 11:49:56 +02:00
David Shah e46e8753c8 frontends/ast: code style 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:55:43 +01:00
David Shah 9b9d24f15b sv: Improve tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah 5501d9090a sv: Fix typedefs in blocks 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00