Eddie Hung
41191f1ea4
Merge pull request #1250 from bwidawsk/master
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techlibs/intel: Clean up Makefile
2019-08-16 14:07:09 -07:00
Eddie Hung
261daffd9d
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-15 12:19:47 -07:00
Eddie Hung
e35dfc5ab5
Only swap ports if $mul and not $__mul
2019-08-13 16:52:15 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef
Add assign PCOUT = P to DSP48E1
2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478
Add DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 10:21:24 -07:00
David Shah
edff79a25a
xilinx: Rework labels for faster Verilator testing
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
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A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Miodrag Milanovic
5f561bdcb1
Proper arith for Anlogic and use standard pass
2019-08-12 20:21:36 +02:00
Miodrag Milanovic
2897fe4d09
Fix formating
2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a
one bit enable signal
2019-08-11 13:59:39 +02:00
Miodrag Milanovic
aa0c37722a
fix mixing signals on FF mapping
2019-08-11 11:40:15 +02:00
Miodrag Milanovic
853c755a0c
Replaced custom step with setundef
2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38
Fixed data width
2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df
Adding new pass to fix carry chain
2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508
cleanup
2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
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Add a few comments to document $alu and $lcu
2019-08-10 09:46:46 +02:00
Eddie Hung
6d254f2de8
Add wreduce to synth_ice40 -dsp as well
2019-08-09 17:05:56 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
041defc5a6
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34
A bit more on where $lcu comes from
2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957
Add more comments
2019-08-09 09:48:17 -07:00
Miodrag Milanovic
d51b135e33
Fix CO
2019-08-09 12:37:10 +02:00
Miodrag Milanovic
7a860c5623
Merge remote-tracking branch 'upstream/master' into efinix
2019-08-09 09:46:37 +02:00
Eddie Hung
1f722b3500
Remove signed from ports in +/xilinx/dsp_map.v
2019-08-08 16:33:20 -07:00
Eddie Hung
2c0be7aa5d
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
Eddie Hung
162eab6b74
Combine techmap calls
2019-08-08 10:55:48 -07:00
Eddie Hung
7160243874
Move xilinx_dsp to before alumacc
2019-08-08 10:45:56 -07:00
Eddie Hung
57b2e4b9c1
INMODE is 5 bits
2019-08-08 10:44:35 -07:00
Eddie Hung
13cc106cf7
Fix copy-pasta typo
2019-08-08 10:44:26 -07:00
Eddie Hung
dae7c59358
Add a few comments to document $alu and $lcu
2019-08-08 10:05:28 -07:00
David Shah
0492b8b541
ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 15:18:59 +01:00
David Shah
cb84ed2326
ecp5: Bring up to date with mul2dsp changes
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 15:14:09 +01:00
David Shah
83b2e02723
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-08 11:40:09 +01:00
David Shah
b8cd4ad64a
DSP48E1 sim model: add SIMD tests
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01
DSP48E1 model: test CE inputs
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8
DSP48E1 sim model: fix seq tests and add preadder tests
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d
DSP48E1 sim model: seq test working
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0
DSP48E1 sim model: Comb, no pre-adder, mode working
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:26:44 +01:00
David Shah
f0f352e971
[wip] sim model testing
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9
[wip] sim model testing
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 09:31:34 +01:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d
Add test
2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74
Remove ice40_unlut
2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
2019-08-07 16:29:38 -07:00
Eddie Hung
a206aed977
Run "opt_expr -fine" instead of "wreduce" due to #1213
2019-08-07 13:59:07 -07:00
Eddie Hung
e3d898dccb
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 13:44:08 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
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ecp5: Make cells_sim.v consistent with nextpnr
2019-08-07 15:35:29 +01:00
David Shah
a36fd8582e
ecp5: Make cells_sim.v consistent with nextpnr
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 14:19:31 +01:00
David Shah
fe95807f16
[wip] DSP48E1 sim model improvements
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 13:09:12 +01:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix
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anlogic : Fix alu mapping
2019-08-07 12:30:52 +02:00
Eddie Hung
e5be9ff871
Fix spacing
2019-08-06 16:47:55 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
David Shah
c43b0c4b49
[wip] DSP48E1 sim model improvements
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 18:47:18 +01:00
David Shah
7a563d0b92
[wip] DSP48E1 sim model improvements
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 13:23:42 +01:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Ben Widawsky
7de098ad45
techlibs/intel: Clean up Makefile
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Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-08-05 11:22:11 -07:00
Miodrag Milanovic
8a3329871b
clock for ram trough gbuf
2019-08-04 12:17:55 +02:00
Miodrag Milanovic
cf96f41c6d
Added bram support
2019-08-04 11:46:36 +02:00
Miodrag Milanovic
837cb0a1b9
anlogic : Fix alu mapping
2019-08-03 14:47:33 +02:00
Miodrag Milanovic
6e210f26fa
Custom step to add global clock buffers
2019-08-03 14:40:23 +02:00
Miodrag Milanovic
ab98f604fd
Initial EFINIX support
2019-08-03 13:10:44 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix
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Fix formatting for msys2 mingw build
2019-08-02 16:37:57 +02:00
Eddie Hung
105aaeaf59
Trim Y_WIDTH
2019-08-01 14:33:16 -07:00
Eddie Hung
65de9aaaa9
Add DSP_SIGNEDONLY back
2019-08-01 14:29:00 -07:00
Eddie Hung
915f4e34bf
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
2019-08-01 13:20:34 -07:00
Eddie Hung
fc0b5d5ab6
Change $__softmul back to $mul
2019-08-01 12:45:14 -07:00
Eddie Hung
332b86491d
Revert "Do not do sign extension in techmap; let packer do it"
...
This reverts commit 595a8f032f
.
2019-08-01 12:17:14 -07:00
Eddie Hung
ed303b07b7
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 12:02:16 -07:00
Eddie Hung
7e86c8bcfb
Fix B_WIDTH > DSP_B_MAXWIDTH case
2019-08-01 10:01:43 -07:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Eddie Hung
d2c33863d0
Do not compute sign bit if result is zero
2019-07-31 16:04:19 -07:00
Eddie Hung
60c4887d15
For signed multipliers, compute sign bit separately...
2019-07-31 15:45:41 -07:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
Eddie Hung
2f71c2c219
Fix spacing
2019-07-26 15:30:51 -07:00
Clifford Wolf
eb663c7579
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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intel: Make -noiopads the default
2019-07-25 17:19:54 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 06:44:17 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Eddie Hung
c39ccc65e9
Add copyright header, comment on cascade
2019-07-24 10:49:09 -07:00
Dan Ravensloft
49528ed3bd
intel: Make -noiopads the default
2019-07-24 10:38:15 +01:00
Eddie Hung
151c5c96c0
Typo for Y_WIDTH
2019-07-23 15:05:20 -07:00
Dan Ravensloft
67b4ce06e0
intel: Map M9K BRAM only on families that have it
...
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
Eddie Hung
cb505c50d3
Remove debug
2019-07-22 16:14:15 -07:00
Eddie Hung
4d71ab384d
Rename according to vendor doc TN1295
2019-07-22 15:08:26 -07:00
Eddie Hung
5e70b8a22b
opt and wreduce necessary for -dsp
2019-07-22 13:48:33 -07:00
Eddie Hung
3a7aeb028d
Use minimum sized width wires
2019-07-22 13:01:26 -07:00