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322 Commits

Author SHA1 Message Date
Miodrag Milanovic 93fbc9fba4 Import module attributes from Verific 2021-10-10 10:01:45 +02:00
Claire Xenia Wolf 34f1df8435 Fixes and add comments for open FIXME items 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 17:24:45 +02:00
Claire Xenia Wolf 1602a03864 Add support for $aldff flip-flops to verific importer 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 16:21:25 +02:00
Miodrag Milanovic abc5700628 verific set db_infer_set_reset_registers 2021-10-04 16:48:33 +02:00
Miodrag Milanovic c3d4bb4cc9 update required verific version 2021-09-02 14:59:16 +02:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
Miodrag Milanovic be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
Miodrag Milanovic 987fca5297 Update to latest verific 2021-07-21 09:46:53 +02:00
Miodrag Milanovic 7a5ac90985 Update to latest Verific with extensions for initial assertions 2021-07-09 09:02:27 +02:00
Miodrag Milanovic 0dbb05a75e Add additional help 2021-07-05 09:16:54 +02:00
Miodrag Milanovic c0d8da20d5 Support command files in Verific 2021-06-16 11:21:44 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Miodrag Milanovic 13c2fd7137 Ganulate Verific support 2021-02-12 10:08:43 +01:00
Miodrag Milanovic d99c032c27 Require latest Verific build 2021-01-30 09:23:46 +01:00
Claire Xenia Wolf acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-01-20 20:48:10 +01:00
Miodrag Milanovic 1c4a18f66f Bump required Verific version 2020-12-02 15:18:04 +01:00
Miodrag Milanovic c228cb74d6 Update verific version 2020-10-30 08:32:59 +01:00
Miodrag Milanovic c8f052bbe0 extend verific library API for formal apps and generators 2020-10-12 14:56:15 +02:00
Miodrag Milanović 1b7ed719a5
Update required Verific version 2020-10-05 13:27:27 +02:00
Miodrag Milanovic a44c5df259 use sha1 for parameter list in case if they contain spaces 2020-09-30 09:16:59 +02:00
Miodrag Milanovic 3f27a4ea68 Use latest verific 2020-09-02 10:22:25 +02:00
Miodrag Milanovic 04d5692a85 Reorder to prevent crash 2020-08-31 12:22:26 +02:00
Miodrag Milanovic 3af499c60f ast recognize lower case x and z and verific gives upper case 2020-08-30 13:33:03 +02:00
Miodrag Milanovic 2f93579bd1 Do not check for 1 and 0 only 2020-08-30 13:15:06 +02:00
Miodrag Milanovic b1e3bc059c Fix import of VHDL enums 2020-08-30 12:25:23 +02:00
Miodrag Milanovic fe8226a22d Add formal apps and template generators 2020-08-26 10:39:57 +02:00
Miodrag Milanovic cc02d58194 Clear last error message 2020-07-29 15:28:33 +02:00
clairexen 3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial 
verific: rewrite initial assume/asserts prior to elaboration
 2020-07-02 17:50:22 +02:00
Miodrag Milanovic 561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Miodrag Milanovic b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
Miodrag Milanovic 4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Miodrag Milanovic f993d18755 verific - import attributes for net buses as well 2020-06-24 11:01:06 +02:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
clairexen b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs 
Do not optimize away FFs in "prep" and Verific front-end
 2020-06-10 12:44:23 +02:00
Miodrag Milanovic d6bec3ba1c verific - detect missing memory to prevent crash. 2020-06-10 11:27:44 +02:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Miodrag Milanovic 71072d1945 Support asymmetric memories for verific frontend 2020-06-01 10:30:03 +02:00
Claire Wolf fa8cb3e35d Revert "Add support for non-power-of-two mem chunks in verific importer" 
This reverts commit 173aa27ca5.
 2020-05-17 11:31:11 +02:00
Eddie Hung 39fa1e160d verific: rewrite initial assume/asserts prior to elaboration 2020-05-15 14:05:28 -07:00
Claire Wolf 173aa27ca5 Add support for non-power-of-two mem chunks in verific importer 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-14 14:38:13 +02:00
Eddie Hung 5017ff4a97 verific: ignore anonymous enums 2020-04-30 07:48:47 -07:00
Eddie Hung 97bfe65d3a verific: support VHDL enums too 2020-04-27 15:17:13 -07:00
Eddie Hung dd5f206d9e verific: recover wiretype/enum attr as part of import_attributes() 2020-04-27 08:43:54 -07:00
Eddie Hung b52eccef3a Revert "verific: import enum attributes from verific" 
This reverts commit 5028e17f7d.
 2020-04-24 11:57:55 -07:00
Eddie Hung d3555c667c verific: do not assert if wire not found; warn instead 2020-04-23 16:28:11 -07:00
Eddie Hung 5028e17f7d verific: import enum attributes from verific 2020-04-22 17:26:56 -07:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Claire Wolf 2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand 
Add Verific support for OPER_REDUCE_NAND
 2020-01-30 19:55:53 +01:00
Claire Wolf 60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help 
`verific` pass to print help message when command syntax error
 2020-01-30 18:05:16 +01:00
Claire Wolf 23c44afaed Add Verific support for OPER_REDUCE_NAND 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-30 18:01:13 +01:00
Eddie Hung f443695a38 Merge remote-tracking branch 'origin/master' into eddie/verific_help 2020-01-27 10:34:10 -08:00
Eddie Hung d730bba6d2 verific: no help() when no YOSYS_ENABLE_VERIFIC 2020-01-27 10:32:18 -08:00
Eddie Hung 7b445121cc verific: also unflatten for 'hierarchy' flow as per @cliffordwolf 2020-01-27 10:15:22 -08:00
Eddie Hung cccc0ae112 verific: unflatten struct ports 2020-01-24 10:12:52 -08:00
Clifford Wolf 22dd9f107c Send people to symbioticeda.com instead of verific.com 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-18 13:06:34 +01:00
Clifford Wolf e93e4a7a2c Improve handling of verific primitives in "verific -import -V" mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 16:00:07 +01:00
Clifford Wolf 55bda2b2c6 Correctly treat empty modules as blackboxes in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-20 12:56:31 +01:00
Clifford Wolf f6ff311a1d Do not rename VHDL entities to "entity(impl)" when they are top modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-20 12:54:10 +01:00
Eddie Hung e2819ce31c Oops 2019-11-19 13:25:38 -08:00
Eddie Hung 84711f0e8c Print help message for verific pass 2019-11-19 13:24:48 -08:00
Clifford Wolf 84982b3083 Improve naming scheme for (VHDL) modules imported from Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-24 12:13:50 +02:00
Clifford Wolf d49c6b2cba Add "verific -L" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-24 09:14:03 +02:00
Clifford Wolf 4033ff8c2e Fix handling of "restrict" in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-21 12:39:28 +02:00
Clifford Wolf 27d59dc055 Fix erroneous ifndef-NDEBUG in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:49:55 +02:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Clifford Wolf 9260e97aa2 Automatically prune init attributes in verific front-end, fixes #1237 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 15:31:49 +02:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Clifford Wolf fc462c8243 Call "read_verilog" with -defer from "read" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:29:36 +02:00
Clifford Wolf 36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Clifford Wolf 2faa1d0e80 Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-30 10:04:26 +02:00
Eddie Hung c7d7d8ad1b For hier_tree::Elaborate() also include SV root modules (bind) 2019-05-03 20:53:25 +02:00
Eddie Hung 3ea54ec400 Fix verific_parameters construction, use attribute to mark top netlists 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Eddie Hung 0f1a4cc03c verific_import() changes to avoid ElaborateAll() 2019-05-03 20:53:25 +02:00
Clifford Wolf 7682629b79 Add "read -verific" and "read -noverific" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 14:03:35 +01:00
Clifford Wolf c863796e9f Fix "verific -extnets" for more complex situations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:17:46 +01:00
Eddie Hung ee013fba54 Update help message for -chparam 2019-03-09 01:56:16 +00:00
Eddie Hung 2aa3903757 Add -chparam option to verific command 2019-03-09 01:54:01 +00:00
Clifford Wolf 60e3c38054 Improve "read" error msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 20:34:42 -08:00
Clifford Wolf a516b4fb5a Check if Verific was built with DB_PRESERVE_INITIAL_VALUE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 19:51:30 +01:00
Clifford Wolf 1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf 50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
Clifford Wolf 3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
Clifford Wolf 910d94b212 Verific updates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:21:50 +01:00
Clifford Wolf 5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 21:03:23 +01:00
Clifford Wolf 9850de405a Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-07 19:48:55 +02:00
Clifford Wolf 4b0448fc2c Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:26:10 +02:00
Clifford Wolf 5d9d22f66d Add "verific -L <int>" option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 20:06:10 +02:00
Clifford Wolf 408077769f Add "verific -work" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 17:22:24 +02:00
Clifford Wolf 4b02ee9162 Add Verific -work parameter 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 13:30:22 +02:00
Clifford Wolf e343f3e6d4 Add "verific -set-<severity> <msg_id>.." 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:49:17 +02:00
Clifford Wolf 0899a53bee Verific workaround for VIPER ticket 13851 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:31:19 +02:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf e275692e84 Verific: Produce errors for instantiating unknown module 
Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 18:44:05 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 5041ed2f7d Fix verific -vlog-incdir and -vlog-libdir handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 18:47:42 +02:00
Clifford Wolf f897af626d Fix "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 16:48:09 +02:00
Clifford Wolf f39b897545 Add "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 15:32:26 +02:00
Clifford Wolf ebf0f003d3 Add "verific -formal" and "read -formal" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 10:02:27 +02:00
Clifford Wolf afedb2d03e Add "read -sv -D" support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:58:15 +02:00
Clifford Wolf 07e616900c Add "read -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:43:38 +02:00
Clifford Wolf 848c3c5c88 Add YOSYS_NOVERIFIC env variable for temporarily disabling verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 20:40:22 +02:00
Clifford Wolf d412b17259 Add simplified "read" command, enable extnets in implicit Verific import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-21 16:56:55 +02:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf 4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf 9a946c207f Add comment to VIPER #13453 work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf 001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf 251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf 4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Clifford Wolf a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Clifford Wolf 617c60cea6 Add PRIM_HDL_ASSERTION support to Verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-07 18:38:42 +02:00
Clifford Wolf 0ac768f9df Fix handling of $global_clocking in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 21:23:47 +02:00
Clifford Wolf 278685b084 Add Verific anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:19:55 +02:00
Clifford Wolf ab8db2c168 Add "verific -autocover" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:10:57 +02:00
makaimann 0c404b1f63 Set RAM runtime flags for Verific frontend 2018-04-05 17:38:08 -07:00
Clifford Wolf 315d5e32bf Fix handling of unclocked immediate assertions in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-26 13:04:10 +02:00
Clifford Wolf 7cf9d88028 Improve import of memories via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-15 18:20:37 +01:00
Clifford Wolf bf402a806a Fix handling of SV compilation units in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-14 20:22:11 +01:00
Clifford Wolf a15208f301 Use Verific hier_tree component for elaboration 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-08 13:26:33 +01:00
Clifford Wolf a4bbfd2d15 Fix Verific handling of "assert property (..);" in always block 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 20:06:02 +01:00
Clifford Wolf 92d5f4db6f Add "verific -import -V" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 19:40:34 +01:00
Clifford Wolf 252627fc54 Set Verific db_preserve_user_nets flag 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 18:08:03 +01:00
Clifford Wolf 480e8e676a Add proper SVA seq.triggered support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 19:29:26 +01:00
Clifford Wolf 261cf706f4 Add VerificClocking class and refactor Verific DFF handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 13:48:53 +01:00
Clifford Wolf 9a2a8cd97b Fixes and improvements in Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 11:40:43 +01:00
Clifford Wolf 3c49e3c5b3 Add $rose/$fell support to Verific bindings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 10:12:15 +01:00
Clifford Wolf 15902d495f Continue refactoring of Verific SVA importer code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 11:45:04 +01:00
Clifford Wolf b6fbeb0969 Add handling of verific OPER_REDUCE_NOR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:26:01 +01:00
Clifford Wolf 2aeb4d4e12 Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:20:27 +01:00
Clifford Wolf 9cd9f5fc78 Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:02:03 +01:00
Clifford Wolf 9d963cd29c Add support for SVA until statements via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 14:57:52 +01:00
Clifford Wolf 5fa2aa2741 Move Verific SVA importer to extra C++ source file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 13:52:49 +01:00
Clifford Wolf c4bf34f6ce Merge Verific SVA preprocessor and SVA importer 2018-02-18 13:28:08 +01:00
Clifford Wolf bc8ab3ab44 Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF 2018-02-15 15:26:37 +01:00
Clifford Wolf 6c00e064e2 Fix single-bit $stable handling in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-01 12:51:49 +01:00
Clifford Wolf 9af40faa0b Add Verific attribute handling for assert/assume/cover/live/fair cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-31 19:06:51 +01:00
Clifford Wolf 1d8161b432 Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-23 17:42:40 +01:00
Clifford Wolf ba90e08398 Add support for Verific PRIM_SVA_NOT properties 2017-12-10 01:10:03 +01:00
Clifford Wolf e4a4c0e10c Add Verific OPER_SVA_STABLE support 2017-12-10 00:59:44 +01:00
Clifford Wolf 27916105a9 Refactoring Verific SVA rewriter 2017-12-10 00:26:26 +01:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 1954c78ea7 Add "verific -vlog-libdir" 2017-10-13 20:23:19 +02:00
Clifford Wolf e7a3c47cc7 Add "verific -vlog-incdir" and "verific -vlog-define" 2017-10-13 20:12:51 +02:00
Clifford Wolf bc5cc4e103 Add Verific fairness/liveness support 2017-10-12 12:00:09 +02:00