mirror of https://github.com/YosysHQ/yosys.git
Fix handling of $global_clocking in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -123,8 +123,11 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
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// FIXME: Parse numeric attributes
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FOREACH_ATTRIBUTE(obj, mi, attr)
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FOREACH_ATTRIBUTE(obj, mi, attr) {
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if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
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continue;
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attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(std::string(attr->Value()));
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}
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}
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RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)
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@ -1955,6 +1958,9 @@ struct VerificPass : public Pass {
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#endif
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}
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if (!verific_error_msg.empty())
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goto check_error;
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if (flatten) {
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for (auto nl : nl_todo)
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nl->Flatten();
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