mirror of https://github.com/YosysHQ/yosys.git
Add $rose/$fell support to Verific bindings
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -1095,7 +1095,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER)
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sva_covers.insert(inst);
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if (inst->Type() == OPER_SVA_STABLE && !mode_nosva)
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if (inst->Type() == OPER_SVA_STABLE)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2Bit(0)->Driver());
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@ -1123,7 +1123,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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continue;
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}
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if (inst->Type() == PRIM_SVA_STABLE && !mode_nosva)
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if (inst->Type() == PRIM_SVA_STABLE)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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@ -1145,7 +1145,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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continue;
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}
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if (inst->Type() == PRIM_SVA_PAST && !mode_nosva)
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if (inst->Type() == PRIM_SVA_PAST)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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@ -1162,6 +1162,25 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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continue;
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}
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if ((inst->Type() == PRIM_SVA_ROSE || inst->Type() == PRIM_SVA_FELL))
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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SigBit sig_d = net_map_at(inst->GetInput1());
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SigBit sig_o = net_map_at(inst->GetOutput());
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SigBit sig_q = module->addWire(NEW_ID);
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if (verific_verbose)
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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module->addEq(NEW_ID, {sig_q, sig_d}, Const(inst->Type() == PRIM_SVA_ROSE ? 1 : 2, 2), sig_o);
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if (!mode_keep)
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continue;
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}
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if (!mode_keep && verific_sva_prims.count(inst->Type())) {
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if (verific_verbose)
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log(" skipping SVA cell in non k-mode\n");
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