mirror of https://github.com/YosysHQ/yosys.git
Add "verific -autocover"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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f10e0e15c5
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ab8db2c168
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@ -99,9 +99,9 @@ string get_full_netlist_name(Netlist *nl)
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// ==================================================================
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VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific) :
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VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover) :
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mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva),
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mode_names(mode_names), mode_verific(mode_verific)
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mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover)
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{
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}
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@ -1279,8 +1279,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if (!mode_nosva)
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{
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for (auto inst : sva_asserts)
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for (auto inst : sva_asserts) {
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if (mode_autocover)
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verific_import_sva_cover(this, inst);
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verific_import_sva_assert(this, inst);
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}
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for (auto inst : sva_assumes)
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verific_import_sva_assume(this, inst);
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@ -1594,6 +1597,9 @@ struct VerificPass : public Pass {
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log(" -extnets\n");
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log(" Resolve references to external nets by adding module ports as needed.\n");
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log("\n");
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log(" -autocover\n");
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log(" Generate automatic cover statements for all asserts\n");
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log("\n");
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log(" -v, -vv\n");
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log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
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log("\n");
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@ -1746,6 +1752,7 @@ struct VerificPass : public Pass {
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std::set<Netlist*> nl_todo, nl_done;
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bool mode_all = false, mode_gates = false, mode_keep = false;
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bool mode_nosva = false, mode_names = false, mode_verific = false;
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bool mode_autocover = false;
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bool flatten = false, extnets = false;
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string dumpfile;
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@ -1778,6 +1785,10 @@ struct VerificPass : public Pass {
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mode_names = true;
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continue;
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}
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if (args[argidx] == "-autocover") {
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mode_autocover = true;
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continue;
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}
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if (args[argidx] == "-V") {
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mode_verific = true;
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continue;
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@ -1930,7 +1941,7 @@ struct VerificPass : public Pass {
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Netlist *nl = *nl_todo.begin();
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if (nl_done.count(nl) == 0) {
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VerificImporter importer(mode_gates, mode_keep, mode_nosva,
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mode_names, mode_verific);
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mode_names, mode_verific, mode_autocover);
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importer.import_netlist(design, nl, nl_todo);
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}
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nl_todo.erase(nl);
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@ -67,8 +67,9 @@ struct VerificImporter
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std::map<Verific::Net*, Verific::Net*> sva_posedge_map;
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bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific;
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bool mode_autocover;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific);
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover);
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RTLIL::SigBit net_map_at(Verific::Net *net);
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