riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,754 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

1200 Commits

Author SHA1 Message Date
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung 8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung 46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
Miodrag Milanovic 0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Eddie Hung ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
Xiretza 6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
whitequark abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
Alberto Gonzalez 6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Eddie Hung 1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
Eddie Hung 60aa804915 tests: fix some test warnings 2020-05-25 10:07:58 -07:00
Eddie Hung 9c6d216a06 tests: add test for abc9 -dff removing a redundant flop entirely 2020-05-25 08:43:33 -07:00
Eddie Hung 8dd93e389e tests: add testcase for abc9 -dff preserving flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 95dcd7e785 test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung 29d84339bf tests: add an generate-else test too 2020-05-25 07:36:53 -07:00
Eddie Hung 589775538c tests: add #2037 testcase 2020-05-25 07:36:53 -07:00
Eddie Hung 33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Eddie Hung e7fd8912f0 tests: attributes before task enable 2020-05-14 16:09:41 -07:00
Eddie Hung 73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 5ad3a85288 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 8d7b3c06b2 abc9: suppress warnings when no compatible + used flop boxes formed 2020-05-14 10:33:56 -07:00
Eddie Hung cdd250ef16 xilinx: update abc9_dff tests 2020-05-14 10:33:56 -07:00
Eddie Hung 762b6ad74a xilinx: remove no-longer-relevant test 2020-05-14 10:33:56 -07:00
Eddie Hung 5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
 2020-05-14 09:45:54 -07:00
Claire Wolf 140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes 
opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
 2020-05-14 18:31:16 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 56a5b1d2da test: add another testcase as per @nakengelhardt 2020-05-14 08:36:36 -07:00
Eddie Hung 5be4b00a0d opt_clean: improve warning message 2020-05-14 00:59:38 -07:00
Eddie Hung aa4a69f89b opt_clean: add init test 2020-05-14 00:31:08 -07:00
Eddie Hung 0d2c33f9f4 tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
Peter Crozier 17f050d3c6 Allow structs within structs. 2020-05-12 17:20:34 +01:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Eddie Hung e5ce5a4fd5 tests: add #2042 testcase 2020-05-11 11:05:19 -07:00
Eddie Hung b11cf67a81 Setup tests/verilog properly 2020-05-11 10:31:02 -07:00
Eddie Hung 49e64ad492 test: update opt_expr_alu test 2020-05-08 11:12:58 -07:00
Eddie Hung 495acf9815 tests: opt_expr tests that depend on consumex 2020-05-08 11:07:11 -07:00