Commit Graph

2031 Commits

Author SHA1 Message Date
Eddie Hung e9bdc86c0e duplicate -> clone 2019-07-12 19:33:02 -07:00
Eddie Hung be0cb7f4b8 More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7d583f9e57 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 83f23a24a8 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 1adbfb5533 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 39a7c7c54c More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 91c07be196 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 399e1ec870 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 58dbb28fd3 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7dc15bdd2d Do not double count cells in abc 2019-07-12 08:22:26 -07:00
Eddie Hung c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
Clifford Wolf fd3d5cefad
Merge pull request #1179 from whitequark/attrmap-proc
attrmap: also consider process, switch and case attributes
2019-07-11 07:23:28 +02:00
whitequark ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Clifford Wolf c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async
Fix clk2fflogic adff reset semantic to negative hold time on reset
2019-07-10 08:48:20 +02:00
Clifford Wolf cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 22:59:51 +02:00
Clifford Wolf 9546ccdbd3 Fix tests/various/async FFL test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Clifford Wolf e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
A new proc_prune pass
2019-07-09 16:59:18 +02:00
Clifford Wolf 38e942507e
Merge pull request #1163 from whitequark/more-case-attrs
More support for case rule attributes
2019-07-09 16:57:16 +02:00
whitequark 44bcb7a187 proc_prune: promote assigns to module connections when legal.
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark 5fe0ffe30f proc_prune: new pass.
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark f2fb958d44 bugpoint: add -assigns and -updates options. 2019-07-09 09:27:43 +00:00
whitequark f7a14a5678 proc_clean: add -quiet option.
This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
Eddie Hung 37b58f4324 Clarify 'wreduce -keepdc' doc 2019-07-08 19:15:07 -07:00
Eddie Hung b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung 3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
whitequark 48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
David Shah d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux
Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-28 14:56:16 -04:00
Eddie Hung 4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Clifford Wolf 1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Eddie Hung a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung 137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung 6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Bogdan Vukobratovic 3225bfb984 Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too 2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic 35fa7b3057 Fix memory leak when one of multiple DFF cells is removed in opt_rmdff
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
2019-06-27 22:02:12 +02:00
Eddie Hung 440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung 6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Bogdan Vukobratovic 0f32cb4e0a Merge remote-tracking branch 'upstream/master' 2019-06-27 12:11:47 +02:00
Clifford Wolf 7c14678ec0 Add "pmux2shiftx -norange", fixes #1135
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 10:59:12 +02:00
Clifford Wolf 69d810e4a8 Fix handling of partial covers in muxcover, fixes #1132
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 09:42:58 +02:00
Eddie Hung c226af3f56 Fix spacing 2019-06-26 20:03:34 -07:00
Eddie Hung 26efd6f0a9 Support more than one port in the abc_scc_break attr 2019-06-26 19:57:54 -07:00
Clifford Wolf 0b7d648c6a Improve opt_clean handling of unused public wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 17:54:17 +02:00
Clifford Wolf 8e9ef891fe Do not clean up buffer cells with "keep" attribute, closes #1128
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 11:01:03 +02:00
Eddie Hung 5db96b8aec Missing muxpack.o in Makefile 2019-06-25 10:38:42 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Clifford Wolf add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung 42720ef6fe Fix spacing 2019-06-25 08:33:17 -07:00
Eddie Hung c4e4902098 Move only one consumer check outside of while loop 2019-06-25 08:29:55 -07:00
Eddie Hung d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung b7deaceadd Walk through as many muxes as exist for rd_en 2019-06-24 18:33:06 -07:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung 545cfbbe0d Cope with $reduce_or common in case 2019-06-21 12:31:14 -07:00
Eddie Hung 15535112b7 Fix spacing 2019-06-21 11:52:51 -07:00
Eddie Hung d89d663c92 Add doc 2019-06-21 11:52:28 -07:00
Eddie Hung 641b86d25f Fix up ExclusiveDatabase with @cliffordwolf's help 2019-06-21 11:45:31 -07:00
Eddie Hung 63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Clifford Wolf ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 19:24:41 +02:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf c9949dba99
Merge pull request #1117 from bwidawsk/more-home
Add a few more filename rewrites
2019-06-21 10:13:51 +02:00
Clifford Wolf 9286b6f013 Add "muxcover -freedecode"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 10:02:10 +02:00
Eddie Hung 54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Clifford Wolf 891ea6512e Improvements in muxcover
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
2019-06-20 19:47:59 -07:00
Clifford Wolf 40188457d1 Add support for partial matches to muxcover, fixes #1091
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 19:47:59 -07:00
Eddie Hung 0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung 9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Ben Widawsky 8767ec3fbd Add a few more filename rewrites
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf 477e566e8d Fix typo, fixes #1095
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:34:52 +02:00
Clifford Wolf 06eb87bcb7 Improve shregmap help message, fixes #1113
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:23:55 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf 11ec7b2aec Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:23:07 +02:00
acw1251 0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung 96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:49:20 +02:00
Eddie Hung 4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung 63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung 7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah 9566573054 ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic 8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic 53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic 291b36afeb Some cleanup, revert sat.cc 2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic 8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Eddie Hung 2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung 90dc4d82de Revert "For 'stat' do not count modules with abc_box_id"
This reverts commit b89bb74452.
2019-06-12 16:51:37 -07:00
Eddie Hung b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00
Eddie Hung 2e7e73f483 Remove hacky wideports_split from abc9 2019-06-12 15:52:49 -07:00
Eddie Hung d9974b85e7 Fix compile errors when #if 1 for debug 2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Eddie Hung 8bb67fa67c Do not call abc9 if no outputs 2019-06-12 10:18:44 -07:00
Eddie Hung 14e870d4c4 More write_xaiger cleanup 2019-06-12 10:00:57 -07:00
Eddie Hung b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung b2c72f74f0 Merge branch 'xc7mux' into xaig 2019-06-12 09:14:27 -07:00
Eddie Hung afd620fd5f Typo: wire delay is -W argument 2019-06-12 09:13:53 -07:00
Eddie Hung 2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
2019-06-12 09:05:02 -07:00
Eddie Hung 882a83c383 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit eaee250a6e, reversing
changes made to 935df3569b.
2019-06-12 09:04:31 -07:00
Eddie Hung 86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
2019-06-12 09:01:15 -07:00
Eddie Hung 1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" 2019-06-12 08:49:15 -07:00
Eddie Hung 4c9fde87d1 Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit 2dffa4685b.
2019-06-12 08:48:45 -07:00
Eddie Hung 2dffa4685b Add "-W' wire delay arg to abc9, use from synth_xilinx 2019-06-11 17:10:47 -07:00
Eddie Hung 6cdea93724 Revert "Try way that doesn't involve creating a new wire"
This reverts commit 2f427acc9e.
2019-06-11 16:05:42 -07:00
Eddie Hung d26646051c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
This reverts commit 5174082208, reversing
changes made to 54379f9872.
2019-06-11 16:05:27 -07:00
Eddie Hung 5174082208 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-11 15:48:41 -07:00
Eddie Hung 2f427acc9e Try way that doesn't involve creating a new wire 2019-06-11 15:48:20 -07:00
Bogdan Vukobratovic 9892df17ef Generate satgen instance instead of calling sat pass 2019-06-11 11:47:13 +02:00
Eddie Hung a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung f19aa8d989 If d_bit already in sigbit_chain_next, create extra wire 2019-06-10 16:16:40 -07:00
Eddie Hung a1d4ae78a0 Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
This reverts commit 94a5f4e609.
2019-06-10 14:34:43 -07:00
Eddie Hung 7d27e1e431 Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
This reverts commit 45d1bdf83a.
2019-06-10 14:34:16 -07:00
Eddie Hung 3579d68193 Revert "Refactor to ShregmapTechXilinx7Static"
This reverts commit e1e37db860.
2019-06-10 14:34:15 -07:00
Eddie Hung b6a39351f4 Revert "Add -tech xilinx_static"
This reverts commit dfe9d95579.
2019-06-10 14:34:14 -07:00
Eddie Hung e1dbeb3004 Revert "Continue support for ShregmapTechXilinx7Static"
This reverts commit 72eda94a66.
2019-06-10 14:34:14 -07:00
Eddie Hung 9d8563178e Revert "shregmap -tech xilinx_static to handle INIT"
This reverts commit 935df3569b.
2019-06-10 14:34:12 -07:00
Eddie Hung 5b999ae68d Elaborate muxpack doc 2019-06-10 10:32:19 -07:00
Eddie Hung 1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung 5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung f705f6a0b5 Comment O(N) -> O(N^2) 2019-06-07 15:39:12 -07:00
Eddie Hung ba52d9b471 Extend ExclusiveDatabase to query SigSpec-s (for $pmux) 2019-06-07 15:34:16 -07:00
Eddie Hung 9b408838f1 Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results 2019-06-07 14:18:17 -07:00
Eddie Hung 887df8914c Resolve @cliffordwolf comment on redundant check 2019-06-07 11:37:52 -07:00
Eddie Hung 5ab59cd59e Resolve @cliffordwolf comment on sigmap 2019-06-07 11:36:19 -07:00
Eddie Hung 30abdaf3b2 Allow muxcover costs to be changed 2019-06-07 08:34:11 -07:00
Eddie Hung fe4394fb9a Allow muxcover costs to be changed 2019-06-07 08:30:39 -07:00
Eddie Hung 2223ca91b0 Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:22:10 -07:00