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yosys
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360 Commits 75 Branches 48 Tags 60 MiB
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360 Commits

Author SHA1 Message Date
Clifford Wolf 2feee7415d Improved edif backend 2013-08-27 14:22:11 +02:00
Clifford Wolf 6685ad436e Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) 2013-08-27 13:12:26 +02:00
Clifford Wolf 5059b31660 Added simple xilinx7 technology mapping files 2013-08-22 20:31:04 +02:00
Clifford Wolf 39ee561169 More explicit integer output in verilog backend 2013-08-22 20:31:04 +02:00
Clifford Wolf 4f4cb2307f Added correct encoding of identifiers in EDIF backend 2013-08-22 14:30:33 +02:00
Clifford Wolf aba8639a3f Added edif backend (still under construction) 2013-08-22 11:34:55 +02:00
Clifford Wolf 8409956c0c Merge pull request #10 from hansiglaser/master 
fixed Verilog parser filename and line numbering issue with include files
 2013-08-21 09:47:06 -07:00
Clifford Wolf f8107ab7fc Some minor documentation fixes 2013-08-21 12:16:44 +02:00
Johann Glaser f352205635 fixed Verilog parser filename and line numbering issue with include files 2013-08-21 09:20:59 +02:00
Clifford Wolf 459e8964fd Merge pull request #9 from hansiglaser/master 
Added support for include directories with the new '-I' argument of the 'read_verilog' command
 2013-08-20 09:38:31 -07:00
Johann Glaser a99c224157 Added support for include directories with the new '-I' argument of the 
'read_verilog' command
 2013-08-20 15:48:16 +02:00
Clifford Wolf 8e31a92407 Merge pull request #8 from hansiglaser/master 
Added support for notif0/notif1 primitives
 2013-08-20 03:36:34 -07:00
Johann Glaser 6c4cbc03c2 Added support for notif0/notif1 primitives 2013-08-20 11:23:59 +02:00
Clifford Wolf e3aa0514f2 Added cleaning of old version_* files to version_* make rule 2013-08-20 10:13:43 +02:00
Clifford Wolf 485e870bcd Added version info to yosys command and added -V option 2013-08-20 09:48:12 +02:00
Clifford Wolf 1af1cebb64 Minor fixes in abc build instructions and abc pass 2013-08-20 09:46:05 +02:00
Clifford Wolf 0003743432 Fixed width and sign detection for ** operator 2013-08-19 20:58:01 +02:00
Clifford Wolf 8656b1c08f Added support for bufif0/bufif1 primitives 2013-08-19 19:50:04 +02:00
Clifford Wolf 4214561890 Improved ast dumping (ast/verilog frontend) 2013-08-19 19:49:14 +02:00
Clifford Wolf a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools 2013-08-15 21:00:06 +02:00
Clifford Wolf 78658199e6 Fixed signed div/mod in const eval (rounding and stuff) 2013-08-15 18:23:42 +02:00
Clifford Wolf 457dc09cdc Added ezsat api for creation of anonymous vectors 2013-08-15 14:40:26 +02:00
Clifford Wolf 2f3da54f26 Added sat -ignore_div_by_zero switch 2013-08-15 11:40:01 +02:00
Clifford Wolf d0e93e04d1 Added eval -brute_force_equiv_checker_x mode 2013-08-15 11:09:30 +02:00
Clifford Wolf 759852914d Added support for "2**n" shifter encoding 2013-08-12 14:47:50 +02:00
Clifford Wolf ccf36cb7d8 Added SAT support for $div and $mod cells 2013-08-11 16:27:15 +02:00
Clifford Wolf a5836af172 Added "clean -purge" and ";;;" support 2013-08-11 13:59:14 +02:00
Clifford Wolf 080f0aac34 Added ";;" as shortcut for "; clean;" 2013-08-11 13:33:38 +02:00
Clifford Wolf 6068b8902f freduce performance fix 2013-08-10 15:03:13 +02:00
Clifford Wolf c8763301b4 Added $div and $mod technology mapping 2013-08-09 17:09:24 +02:00
Clifford Wolf 376150c926 Added techmap -opt mode 2013-08-09 15:20:22 +02:00
Clifford Wolf 05483619f0 Some fixes to improve determinism 2013-08-09 12:42:32 +02:00
Clifford Wolf d97782b848 Sort ctrl signals in fsm_extract 2013-08-08 15:46:00 +02:00
Clifford Wolf 6a40e46a04 Added -try option to freduce pass 2013-08-08 10:56:27 +02:00
Clifford Wolf 8cd153612e Added "clean" command (less verbose opt_clean) 2013-08-08 10:53:37 +02:00
Clifford Wolf 56e01ce389 Fixed topological ordering in freduce pass 2013-08-07 19:38:19 +02:00
Clifford Wolf e729857647 Improved handling of private names in opt_clean and rename commands 2013-08-07 18:39:49 +02:00
Clifford Wolf 3f5d7df603 Added stubnets example to manual prog chapter 2013-08-07 02:19:35 +02:00
Clifford Wolf 653750faac Small bugfixes in freduce pass 2013-08-06 15:53:09 +02:00
Clifford Wolf 6efca9ea5a Added freduce command 2013-08-06 15:04:52 +02:00
Clifford Wolf 117489f95a Fixed SigPool::del() method 2013-08-06 15:04:24 +02:00
Clifford Wolf ff965424c2 Added proper deallocation of history buffer 2013-08-06 15:03:46 +02:00
Clifford Wolf 8b2f7792ba Updated TODO section in README 2013-08-01 20:02:15 +02:00
Clifford Wolf 0f38008ed3 Added "design" command (-reset, -save, -load) 2013-07-27 14:27:51 +02:00
Clifford Wolf 974b6a947c Added "help -write-web-command-reference-manual" 2013-07-26 00:01:31 +02:00
Clifford Wolf 98906b211c Fixed comments in manual rtlil/ilang syntax 2013-07-25 15:01:02 +02:00
Clifford Wolf 36c39cbd04 Added RTLIL and Liberty syntax highlighting to manual 2013-07-25 14:00:16 +02:00
Clifford Wolf 88d0829d65 Automatically run "proc" on extract map files 2013-07-24 20:19:08 +02:00
Clifford Wolf ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
Clifford Wolf d815f1c770 Fixed "make clean" for manual files 2013-07-23 14:19:47 +02:00