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760 Commits

Author SHA1 Message Date
Clifford Wolf 56c00e871f Remove old $pmux_safe code from write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-17 11:49:04 +02:00
whitequark 4ff44d85a5 write_verilog: dump zero width constants correctly. 
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
 2019-07-16 21:00:09 +00:00
N. Engelhardt ab4b9e8db4 smt: handle failure of setrlimit syscall 2019-07-15 23:33:18 +08:00
Clifford Wolf 9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark 
write_verilog: write RTLIL::Sa aka - as Verilog ?
 2019-07-11 07:25:52 +02:00
Eddie Hung 375fcbe511 abc_flop to also get topologically sorted 2019-07-10 20:26:09 -07:00
Eddie Hung ea6ffea2cd Fix clk_pol for FD*_1 2019-07-10 20:10:20 -07:00
Eddie Hung e603d719d6 Fix spacing 2019-07-10 19:04:22 -07:00
Eddie Hung 4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung a092c48f03 Use split_tokens() 2019-07-10 17:34:51 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Clifford Wolf 6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 
write_verilog: fix placement of case attributes
 2019-07-09 22:51:25 +02:00
whitequark 37bb6b5e96 write_verilog: fix placement of case attributes. NFC. 2019-07-09 19:14:03 +00:00
whitequark 6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. 
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
 2019-07-09 18:35:49 +00:00
Eddie Hung 00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore 
Rename __builtin_bswap32 -> bswap32
 2019-07-09 10:22:57 -07:00
Eddie Hung 5a0f2e43c7 Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
whitequark 628437b01c verilog_backend: dump attributes on SwitchRule. 
This appears to be an omission.
 2019-07-08 15:11:29 +00:00
whitequark 55c1f40277 verilog_backend: dump attributes on CaseRule, as comments. 
Attributes are not permitted in that position by Verilog grammar.
 2019-07-08 12:48:50 +00:00
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Eddie Hung 10524064e9 write_xaiger to treat unknown cell connections as keep-s 2019-07-02 19:14:30 -07:00
Eddie Hung 69f4c039ce Safe side: all flops have different mergeability class 2019-07-02 12:21:03 -07:00
Eddie Hung a31e17182d Refactor and cope with new abc_flop format 2019-07-01 11:50:34 -07:00
Eddie Hung 699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Eddie Hung 38d8806bd7 Add generic __builtin_bswap32 function 2019-06-28 09:59:47 -07:00
Eddie Hung 524af21317 Also fix write_aiger for UB 2019-06-28 09:55:07 -07:00
Eddie Hung 36e2eb06bb Fix more potential for undefined behaviour due to container invalidation 2019-06-28 09:51:43 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung 080a5ca536 Improve debugging message for comb loops 2019-06-26 20:02:38 -07:00
Eddie Hung cec2292b0b Merge remote-tracking branch 'origin/master' into xaig 2019-06-24 20:01:43 -07:00
Eddie Hung 7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung fddb027cab Replace assert with error message 2019-06-21 17:18:04 -07:00
Eddie Hung 7074ec9cd5 Add log_push()/log_pop() inside write_xaiger 2019-06-21 17:17:29 -07:00
Eddie Hung 65c1199acd One more workaround for gcc-4.8 2019-06-21 14:36:24 -07:00
Eddie Hung bd7ec673dd No point logging constant bit 2019-06-21 14:31:09 -07:00
Eddie Hung 70c93ea0c4 Move comment 2019-06-21 14:31:09 -07:00
Miodrag Milanovic fde90f7f8e Fix json formatting 2019-06-21 20:01:40 +02:00
Miodrag Milanovic 50e7221077 Add upto and offset to JSON ports 2019-06-21 19:47:25 +02:00
Clifford Wolf f15def325c Added JSON upto and offset 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 15:22:17 +02:00
Eddie Hung 6a336ca23e Fix spacing 2019-06-20 22:30:20 -07:00
Eddie Hung e21f01d938 Refactor bit2aig for less lookups 2019-06-20 22:10:43 -07:00
Eddie Hung 4422b7311b Fix gcc invalidation behaviour for write_aiger 2019-06-20 22:10:43 -07:00
Eddie Hung 32f8014e12 Fix gcc error, due to dict invalidation during recursion 2019-06-20 22:10:43 -07:00
Eddie Hung c4ea6fff65 Fix gcc invalidation behaviour for write_aiger 2019-06-20 21:56:47 -07:00
Eddie Hung 8e56cfb6bb write_xaiger to flatten 1'bx/1'bz to 1'b0 again 2019-06-20 19:41:27 -07:00
Eddie Hung ad36eb24c0 Fix different abc9 test 2019-06-20 19:41:27 -07:00
Eddie Hung 9faeba7a66 Fix broken abc9.v test due to inout being 1'bx 2019-06-20 19:41:27 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 4e5836a5fb Handle COs driven by 1'bx 2019-06-20 17:38:04 -07:00
Eddie Hung f2d541962e write_xaiger to skip POs driven by 1'bx 2019-06-20 17:37:54 -07:00
Ben Widawsky 4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00
Clifford Wolf c23bbc4291 Add timescale and generated-by header to yosys-smtbmc MkVcd 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-16 23:12:03 +02:00
Eddie Hung 0c59bc0b75 Cleanup 2019-06-16 10:42:00 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 6852c83bbe Cleanup write_xaiger 2019-06-15 22:50:15 -07:00
Eddie Hung bd2690e9b9 Preserve init of flops, and write into XAIG 2019-06-15 22:41:13 -07:00
Eddie Hung 2309459605 Do not treat $__ABC_FF_ as a user cell 2019-06-15 19:36:55 -07:00
Eddie Hung 0debea25a7 Update comment 2019-06-15 18:24:04 -07:00
Eddie Hung c2f3f116d0 Use $__ABC_FF_ instead of $_FF_ 2019-06-15 18:16:14 -07:00
Eddie Hung 6d74b3e004 Update comment 2019-06-15 09:36:02 -07:00
Eddie Hung 357d36ef4f write_xaiger to treat abc_flop boxes as boxff for ABC 2019-06-15 09:07:03 -07:00
Eddie Hung 7ff8330d1e Leave breadcrumb behind 2019-06-14 13:34:40 -07:00
Eddie Hung 46e69ee934 Remove redundant condition 2019-06-14 13:31:18 -07:00
Eddie Hung 9b55e69755 Revert "Cleanup/optimise toposort in write_xaiger" 
This reverts commit 1948e7c846.

Restores old toposort with optimisations
 2019-06-14 13:29:36 -07:00
Eddie Hung 746f70a9ce Update comment 2019-06-14 13:10:46 -07:00
Eddie Hung 0fa6a441f1 Check that whiteboxes are synthesisable 2019-06-14 13:08:38 -07:00
Eddie Hung 2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung 7876b5b8be Cover __APPLE__ too for little to big endian 2019-06-14 12:40:51 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 97d2656375 Resolve comments from @daveshah1 2019-06-14 12:00:02 -07:00
Eddie Hung ee428f73ab Remove WIP ABC9 flop support 2019-06-14 10:37:52 -07:00
Eddie Hung 1656c44373 Cleanup 2019-06-14 10:29:27 -07:00
Eddie Hung 751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung 1948e7c846 Cleanup/optimise toposort in write_xaiger 2019-06-14 10:13:17 -07:00
David Shah 9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Eddie Hung 8374eb1cb4 Remove unnecessary undriven_bits.insert 2019-06-12 15:55:02 -07:00
Eddie Hung fb2758aade write_xaiger to preserve POs even if driven by constant 2019-06-12 15:44:30 -07:00
Eddie Hung 2e7b3eee40 Add a couple more tests 2019-06-12 15:43:43 -07:00
Eddie Hung 14e870d4c4 More write_xaiger cleanup 2019-06-12 10:00:57 -07:00
Eddie Hung 4be417f6e1 Cleanup write_xaiger 2019-06-12 09:53:14 -07:00
Eddie Hung b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung 7b186740d3 Add log_assert to ensure no loops 2019-06-04 12:01:25 -07:00
Eddie Hung 1b836c93bb Only toposort builtin and abc types 2019-06-04 11:56:58 -07:00
Eddie Hung 257f7ff5f6 When creating new holes cell, inherit parameters too 2019-06-03 12:30:54 -07:00
Eddie Hung 4623177655 ABC9 to understand flops 2019-05-31 15:23:33 -07:00
Eddie Hung eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Eddie Hung 887c31f33b Fix issue where keep signal became PI, but also box was adding CI driver 2019-05-30 16:03:22 -07:00
Eddie Hung e3c8132d7a Do not re-sort box_module ports 2019-05-30 12:26:51 -07:00
Eddie Hung fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Eddie Hung 1423384367 Fix abc_test024 2019-05-29 15:24:09 -07:00
Eddie Hung b4321a31bb Fix for abc9_test022 2019-05-28 12:42:17 -07:00
Eddie Hung 13e233217c Small improvement 2019-05-28 11:29:59 -07:00
Eddie Hung 914074a07c Update from master 2019-05-28 09:35:45 -07:00
Eddie Hung 3f60061615 Map file to include boxes not CI/CO 2019-05-27 23:10:59 -07:00
Eddie Hung 234156c01a Instantiate cell type (from sym file) otherwise 'clean' warnings 2019-05-27 12:16:10 -07:00
Eddie Hung 03b289a851 Add 'cinput' and 'coutput' to symbols file for boxes 2019-05-27 11:38:52 -07:00
Eddie Hung 3c8368454f Fix "a" connectivity 2019-05-26 14:14:13 -07:00
Eddie Hung 67f7c64a77 Fix padding, remove CIs from undriven_bits before erasing undriven POs 2019-05-26 11:26:38 -07:00
Eddie Hung 32a4c10c0d Fix "a" extension 2019-05-26 02:44:36 -07:00
Eddie Hung 01684643b6 Fix "write_xaiger", and to write each box contents into holes 2019-05-25 22:34:50 -07:00