mirror of https://github.com/YosysHQ/yosys.git
Only toposort builtin and abc types
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@ -181,14 +181,17 @@ struct XAigerWriter
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for (auto cell : module->cells())
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{
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RTLIL::Module* inst_module = module->design->module(cell->type);
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bool known_type = yosys_celltypes.cell_known(cell->type);
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bool builtin_type = yosys_celltypes.cell_known(cell->type);
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bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id");
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if (!holes_mode) {
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toposort.node(cell->name);
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for (const auto &conn : cell->connections())
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{
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for (const auto &conn : cell->connections()) {
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if (!builtin_type && !abc_type)
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continue;
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if (!cell->type.in("$_NOT_", "$_AND_")) {
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if (known_type) {
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if (builtin_type) {
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if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
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continue;
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if (cell->type == "$memrd" && conn.first == "\\DATA")
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@ -199,8 +202,8 @@ struct XAigerWriter
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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if (inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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}
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}
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