Salvador E. Tropea
ca23554528
Excluded $_TBUF_ from opt_merge pass
2017-07-03 13:21:20 -03:00
Clifford Wolf
0a02cdb93b
Fix and_or_buffer optimization in opt_expr for signed operators
2017-07-01 16:05:26 +02:00
Clifford Wolf
0f217080cf
Add "design -import"
2017-06-30 19:18:52 +02:00
Clifford Wolf
8952bd6f45
Add chtype command
2017-06-30 17:57:34 +02:00
Clifford Wolf
18c030a8c9
Add $tribuf to opt_merge blacklist
2017-06-30 17:44:44 +02:00
Clifford Wolf
155a80dfb7
Fix handling of init values in "abc -dff" and "abc -clk"
2017-06-20 15:32:23 +02:00
Clifford Wolf
f6421c83a2
Switched abc "clock domain not found" error to log_cmd_error()
2017-06-20 04:22:34 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
9ed4c9d710
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
Clifford Wolf
fad52abf70
Add aliases for common sets of gate types to "abc -g"
2017-05-24 11:39:05 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
3bbac5c141
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
dee4ec1661
Fix gcc compiler warning
2017-04-05 11:21:06 +02:00
Clifford Wolf
180d704568
Disable opt_merge for $anyseq and $anyconst
2017-02-28 22:17:00 +01:00
Clifford Wolf
1a6c02a532
Add "chformal -assert2assume" and friends
2017-02-28 00:00:44 +01:00
Clifford Wolf
db7fc0e32d
Add "chformal" pass
2017-02-27 13:25:28 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
Clifford Wolf
69468d5a16
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
Clifford Wolf
db7314bc02
Fix techmap for inout ports connected to inout ports
2017-02-13 16:55:25 +01:00
Clifford Wolf
76c4ee096b
Do not eagerly fix port widths on parameterized cells
2017-02-12 17:42:57 +01:00
Clifford Wolf
95dae6d416
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
Clifford Wolf
a5bfeb9e07
Add optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 10:05:00 +01:00
C-Elegans
94b272077d
Fix issue #306 , "Bug in opt -full"
...
Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
2017-02-10 10:38:02 -05:00
Clifford Wolf
e6cc67b46f
Fix handling of init attributes with strange width
2017-02-09 16:06:58 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
8927e19b13
Update ABC scripts to use "&nf" instead of "map"
2017-02-01 11:15:20 +01:00
Clifford Wolf
ffbe8d41f3
Fix indenting and log messages in code merged from opt_compare_pr
2017-01-31 16:20:56 +01:00
Clifford Wolf
19a980277f
Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr
2017-01-31 15:54:41 +01:00
Clifford Wolf
7481ba4750
Improve opt_rmdff support for $dlatch cells
2017-01-31 10:15:04 +01:00
C-Elegans
a94c3694d7
Refactor and generalize the comparision optimization
...
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
2017-01-30 17:52:16 -05:00
Clifford Wolf
fe29869ec5
Add $ff and $_FF_ support to equiv_simple
2017-01-30 10:50:38 +01:00
Clifford Wolf
45e10c1c89
Be more conservative with merging large cells into FSMs
2017-01-26 09:19:28 +01:00
Clifford Wolf
49b8160488
Add warnings for quickly growing FSM table size in fsm_expand
2017-01-26 09:05:59 +01:00
C-Elegans
2fa0fd4a37
Do not use b.as_int() in calculation of bit set
2017-01-21 12:58:26 -05:00
C-Elegans
84f9cd0025
Optimize compares to powers of 2
...
Remove opt_compare and put comparison pass in opt_expr
assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a < (1<<x) becomes !a[7:x]
Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false
delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd
(remove opt_compare step)
2017-01-16 13:45:50 -05:00
Austin Seipp
6781543244
passes/hierarchy: delete some dead code
...
Signed-off-by: Austin Seipp <aseipp@pobox.com>
2017-01-15 16:39:12 -06:00
C-Elegans
943389cdd5
Fix issue #269 , optimize signed compare with 0
...
add opt_compare pass and add it to opt
for a < 0:
if a is signed, replace with a[max_bit-1]
for a >= 0:
if a is signed, replace with ~a[max_bit-1]
2017-01-15 13:38:29 -05:00
Clifford Wolf
0cac95ea94
Added "check -initdrv"
2017-01-04 18:12:41 +01:00
Clifford Wolf
f0df7dd796
Added cell port resizing to hierarchy pass
2017-01-01 23:03:44 +01:00
Clifford Wolf
b1cdf772eb
Added "design -reset-vlog"
2016-11-30 11:25:55 +01:00
Clifford Wolf
ac7a175a3c
Improved equiv_purge log output
2016-11-29 13:30:35 +01:00
Clifford Wolf
e444e59963
Added wire start_offset and upto handling to splitnets cmd
2016-11-23 13:54:33 +01:00
Clifford Wolf
55785a96eb
Improved ABC default scripts
2016-11-19 18:20:54 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
1827a48964
Minor bugfix in submod
2016-11-09 13:13:26 +01:00
Clifford Wolf
97ac77513f
Bugfix in "setundef" pass
2016-11-08 18:53:36 +01:00
Clifford Wolf
ef603c6fe1
Implemented "scc -set_attr"
2016-11-06 00:04:10 +01:00
Clifford Wolf
914aa8a5d3
Bugfix in "scc" command
2016-11-06 00:03:35 +01:00
Clifford Wolf
308a4b4a1b
Bugfix in "hierarchy -check"
2016-11-02 20:09:57 +01:00
Clifford Wolf
b63cace90f
Added support for fsm_encoding="user"
2016-11-02 13:15:49 +01:00
Clifford Wolf
0c8e973d32
Added "fsm_expand -full"
2016-11-02 09:31:39 +01:00
Clifford Wolf
d9d38eeedb
Bugfix in fsm_map for FSMs without reset state
2016-10-25 23:21:37 +02:00
Clifford Wolf
aa72262330
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
Clifford Wolf
3655d7fea7
Added "setparam -type"
2016-10-19 13:54:04 +02:00
Clifford Wolf
15fb56697a
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
Clifford Wolf
6425d34e73
Added clk2fflogic support for $dffsr and $dlatch
2016-10-17 13:28:55 +02:00
Clifford Wolf
3a09d6bb65
Improvements and bugfixes in clk2fflogic
2016-10-16 23:03:29 +02:00
Clifford Wolf
74702b04c2
Build fixes for VS 2015
2016-10-16 20:37:02 +02:00
Clifford Wolf
fa535c0b00
Some minor build fixes for Visual C
2016-10-14 18:36:02 +02:00
Clifford Wolf
e4c5ee9b89
Avoid using strcasecmp()
2016-10-14 18:20:36 +02:00
Clifford Wolf
2733994aeb
Added clk2fflogic
2016-10-14 14:55:07 +02:00
Clifford Wolf
2ef454c3f5
Added opt_rmdff support for $ff cells
2016-10-14 13:02:36 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
ffbb4e992e
Added MEMID handling to "flatten" pass
2016-10-14 10:36:37 +02:00
Clifford Wolf
ee91350add
Added "zinit" pass
2016-10-12 12:05:19 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
ed519f578e
Added "opt_rmdff -keepdc"
2016-09-30 17:02:38 +02:00
Clifford Wolf
e788ad4885
Cosmetic fix in test_autotb.cc
2016-09-19 20:43:43 +02:00
Clifford Wolf
5e155aa121
Avoid creating very long strings in test_autotb
2016-09-19 10:20:20 +02:00
Clifford Wolf
d8ad889594
Bugfix in techmap parameter handling
2016-09-14 20:46:54 +02:00
Kaj Tuomi
df4ab169a7
Typo fix.
2016-09-08 10:57:16 +03:00
Clifford Wolf
cb7dbf4070
Improvements in assertpmux
2016-09-07 12:42:16 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
f3f5a02045
Added "tee +INT -INT"
2016-09-06 17:43:24 +02:00
Clifford Wolf
fc5281b3f7
Run log_flush() before solving in sat command
2016-09-06 17:35:25 +02:00
Clifford Wolf
4ea7054b56
Improved init spec handling in opt_rmdff, modernized the code a bit
2016-08-30 01:34:04 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
66582964bc
Improved "show" help message
2016-08-28 12:34:36 +02:00
Clifford Wolf
23afeadb5e
Fixed handling of transparent bram rd ports on ROMs
2016-08-27 17:06:22 +02:00
Clifford Wolf
cad40fc874
Fixed bug in memory_share for memory ports with different ABITS
2016-08-22 14:26:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
b3a01451a5
Bugfix in test_autotb
2016-08-18 13:43:12 +02:00
Clifford Wolf
00f29d5e5c
Fixed use-after-free dict<> usage pattern in hierarchy.cc
2016-08-16 09:07:13 +02:00
Clifford Wolf
321e15b0bf
Minor fixes in show command
2016-08-16 00:36:24 +02:00
Clifford Wolf
73b7232ec8
Fixed some compiler warnings in attrmap command
2016-08-10 13:44:08 +02:00
Clifford Wolf
b0aab4e304
Added "attrmap" command
2016-08-09 19:56:55 +02:00
Clifford Wolf
3c6d31fd06
Added "attrmvcp" pass
2016-08-09 11:18:48 +02:00
Clifford Wolf
9d15529214
Undo "preserve wire attributes in iopadmap" change (it was OK before)
2016-08-08 11:47:35 +02:00
Clifford Wolf
88a67afa7d
Added "test_autotb -seed" (and "autotest.sh -S")
2016-08-06 13:32:29 +02:00
Clifford Wolf
90c17aad56
preserve wire attributes in iopadmap
2016-08-06 13:24:59 +02:00
Clifford Wolf
5d6765a9d2
Added "insbuf" command
2016-08-02 10:37:19 +02:00
Clifford Wolf
8537c4d206
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56
Improvements in CellEdgesDatabase
2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2
Added CellEdgesDatabase API
2016-07-24 13:59:57 +02:00
Clifford Wolf
54966679df
Moved SatHelper::setup_init() code to SatHelper::setup()
2016-07-24 12:18:39 +02:00
Clifford Wolf
34e833103b
Added $initstate support to "sat" command
2016-07-23 17:01:03 +02:00