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546 Commits

Author SHA1 Message Date
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 042b67f024 No limit for length of lines in BLIF front-end 2016-10-19 12:44:58 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 8f5bf6de32 Added liberty parser support for types within cell decls 2016-09-23 13:53:23 +02:00
Clifford Wolf aaa99c35bd Added $past, $stable, $rose, $fell SVA functions 2016-09-19 01:30:07 +02:00
Clifford Wolf 13a03b84d4 Added support for bus interfaces to "read_liberty -lib" 2016-09-18 18:48:59 +02:00
Clifford Wolf ab18e9df7c Added assertpmux 2016-09-07 00:28:01 +02:00
Clifford Wolf d55a93b39f Bugfix in parsing of BLIF latch init values 2016-09-06 17:35:06 +02:00
Clifford Wolf 97583ab729 Avoid creation of bogus initial blocks for assert/assume in always @* 2016-09-06 17:34:42 +02:00
Clifford Wolf aa25a4cec6 Added $anyconst support to yosys-smtbmc 2016-08-30 19:27:42 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 1276c87a56 Added read_verilog -norestrict -assume-asserts 2016-08-26 23:35:27 +02:00
Clifford Wolf 4be4969bae Improved verilog parser errors 2016-08-25 11:44:37 +02:00
Clifford Wolf cd18235f30 Added SV "restrict" keyword 2016-08-24 15:30:08 +02:00
Clifford Wolf 450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf 82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf dbdd8927e7 Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() 2016-08-21 13:18:09 +02:00
Clifford Wolf fe9315b7a1 Fixed finish_addr handling in $readmemh/$readmemb 2016-08-20 13:47:46 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf e9fe57c75e Only allow posedge/negedge with 1 bit wide signals 2016-08-10 19:32:11 +02:00
Clifford Wolf 7f755dec75 Fixed bug in parsing real constants 2016-08-06 13:16:23 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf 5b944ef11b Fixed a verilog parser memory leak 2016-07-25 16:37:58 +02:00
Clifford Wolf 7a67add95d Fixed parsing of empty positional cell ports 2016-07-25 12:48:03 +02:00
Clifford Wolf 9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf 7fef5ff104 Using $initstate in "initial assume" and "initial assert" 2016-07-21 14:37:28 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Clifford Wolf 9bca8ccd40 Merge branch 'sv_packages' of https://github.com/rubund/yosys 2016-06-19 15:48:40 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Clifford Wolf 9e28290b0f Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 766032c5f8 Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} 2016-05-27 17:55:03 +02:00
Clifford Wolf ee071586c5 Fixed access-after-delete bug in mem2reg code 2016-05-27 17:25:33 +02:00
Clifford Wolf e9ceec26ff fixed typos in error messages 2016-05-27 16:37:36 +02:00
Clifford Wolf 060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Clifford Wolf 570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf 779e2cc819 Added support for "active high" and "active low" latches in BLIF front-end 2016-04-22 18:02:55 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 5328a85149 Do not set "nosync" on task outputs, fixes #134 2016-03-24 12:16:47 +01:00
Clifford Wolf 4f0d4899ce Added support for $stop system task 2016-03-21 16:19:51 +01:00
Clifford Wolf e5d42ebb4d Added $display %m support, fixed mem leak in $display, fixes #128 2016-03-19 11:51:13 +01:00
Clifford Wolf ef4207d5ad Fixed localparam signdness, fixes #127 2016-03-18 12:15:00 +01:00
Clifford Wolf b6d08f39ba Set "nosync" attribute on internal task/function wires 2016-03-18 10:53:29 +01:00
Clifford Wolf 33c10350b2 Fixed Verilog parser fix and more similar improvements 2016-03-15 12:22:31 +01:00
Andrew Becker 81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. 2016-03-15 12:03:40 +01:00
Clifford Wolf 35a6ad4cc1 Fixed typos in verilog_defaults help message 2016-03-10 11:14:51 +01:00
Clifford Wolf 22c549ab37 Fixed BLIF parser for empty port assignments 2016-02-24 09:16:43 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 7bd329afa0 Support for more Verific primitives (patch I got per email) 2016-02-13 08:19:30 +01:00
Clifford Wolf 6a27cbe5b1 Bugfix in Verific front-end 2016-02-03 08:59:57 +01:00
Clifford Wolf 4a3e1ded1e Updated verific build instructions 2016-02-02 19:50:17 +01:00
Clifford Wolf ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Rick Altherr 34969d4140 genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree() 2016-01-31 09:20:16 -08:00
Clifford Wolf 5e90a78466 Various improvements in BLIF front-end 2015-12-20 13:12:24 +01:00
Clifford Wolf 4a697accd4 Fixed oom bug in ilang parser 2015-11-29 20:30:32 +01:00
Clifford Wolf 32f5ee117c Fixed performance bug in ilang parser 2015-11-27 19:46:47 +01:00
Clifford Wolf ab2d8e5c8c Added PRIM_DLATCHRS support to verific front-end 2015-11-24 12:16:19 +01:00
Clifford Wolf c86fbae3d1 Fixed handling of re-declarations of wires in tasks and functions 2015-11-23 17:09:57 +01:00
Clifford Wolf 415e0a1b90 Fixed performance bug in Verific importer 2015-11-16 12:38:56 +01:00
Clifford Wolf b18f3a2974 Changes for Verific 3.16_484_32_151112 2015-11-12 19:28:14 +01:00
Clifford Wolf 7ae3d1b5a9 More bugfixes in handling of parameters in tasks and functions 2015-11-12 13:02:36 +01:00
Clifford Wolf 34f2b84fb6 Fixed handling of parameters and localparams in functions 2015-11-11 10:54:35 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
Clifford Wolf f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf e51dcc83d0 Fixed complexity of assigning to vectors in constant functions 2015-10-01 12:15:35 +02:00
Clifford Wolf 9caeadf797 Fixed detection of unconditional $readmem[hb] 2015-09-30 15:46:51 +02:00
Clifford Wolf f9d7df0869 Bugfixes in $readmem[hb] 2015-09-25 13:49:48 +02:00
Clifford Wolf b2544cfcf7 Fixed segfault in AstNode::asReal 2015-09-25 12:38:01 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 1b8cb9940e Fixed AstNode::mkconst_bits() segfault on zero-sized constant 2015-09-24 11:21:20 +02:00
Clifford Wolf e2e092b144 Added read_verilog -nodpi 2015-09-23 08:23:38 +02:00
Clifford Wolf 089c1e176f Bugfix in handling of multi-dimensional memories 2015-09-23 07:56:17 +02:00
Clifford Wolf 559929e341 Warning for $display/$write outside initial block 2015-09-23 07:16:03 +02:00
Clifford Wolf b845b77f86 Fixed support for $write system task 2015-09-23 07:10:56 +02:00
Clifford Wolf a3a13cce32 Fixed detection of "task foo(bar);" syntax error 2015-09-22 21:34:21 +02:00
Clifford Wolf 6176f4d081 Fixed multi-level prefix resolving 2015-09-22 20:52:02 +02:00
Clifford Wolf 4b8200eb49 Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Andrew Zonenberg c469f22144 Improvements to $display system task 2015-09-19 10:33:37 +02:00
Clifford Wolf 9db05d17fe Added AST_INITIAL checks for $finish and $display 2015-09-18 09:50:57 +02:00
Andrew Zonenberg 7141f65533 Initial implementation of $display() 2015-09-18 09:36:46 +02:00
Andrew Zonenberg e446e651cb Initial implementation of $finish() 2015-09-18 09:30:25 +02:00
Clifford Wolf b10ea0550d gcc-4.6 build fixes 2015-09-01 12:51:23 +02:00
Clifford Wolf eb38722e98 Fixed handling of memory read without address 2015-08-22 14:46:42 +02:00
Clifford Wolf a7ab9172f9 Small corrections to const2ast warning messages 2015-08-17 16:22:53 +02:00
Florian Zeitz 0491042849 Check base-n literals only contain valid digits 2015-08-17 15:37:33 +02:00
Florian Zeitz 64ccbf8510 Warn on literals exceeding the specified bit width 2015-08-17 15:27:35 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Larry Doolittle 022f570563 Keep gcc from complaining about uninitialized variables 2015-08-14 23:26:49 +02:00