4191 Commits

Author	SHA1	Message	Date
Chun Lin Min	acddc36389	add PolarFire FPGA support	2024-07-02 12:44:30 -07:00
Catherine	580aaa362d	opt_lut_ins: fix name of global object. NFCI	2024-06-28 15:12:36 +00:00
Emil J. Tywoniak	01f332e750	opt_expr: reduce mostly harmless warning to log	2024-06-25 20:18:49 +02:00
Martin Povišer	fa4a2b6b0d	opt_expr: In clkinv loop ignore irrelevant cells early ... Each call to `handle_clkpol_celltype_swap` has a conversion of the cell's type ID to an allocated string. This can sum up to a non-negligible time being spent in the clkpol code even for a design which doesn't have any flip-flop gates.	2024-06-24 18:32:33 +02:00
Martin Povišer	7a8a69b65c	opt_expr: Revisit sorting in `replace_const_cells` ... Avoid building a cell-to-inbit map when sorting the cells, add a warning if we are unable to sort, and move the code treating non-combinational cells ahead of the rest (this means we don't need to pass non-combinational cells to the TopoSort object at all).	2024-06-24 18:32:33 +02:00
Philippe Sauter	2f0f10cb87	peepopt: limit padding from shiftadd ... The input to a shift operation is padded. This reduced the final number of MUX cells but during techmap it can create huge temporary multiplexers in the log shifter. This significantly increases runtime and resources. A limit is added with a warning when it is used.	2024-06-14 15:33:03 +02:00
Philippe Sauter	74e504330a	peepopt: fix sign check in shiftadd	2024-06-14 13:01:18 +02:00
phsauter	34b5c6d062	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
Miodrag Milanovic	9b82a44d25	Fix help message typo	2024-06-07 08:26:59 +02:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive ... box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	b230c95cc4	select: Adjust help	2024-05-29 20:41:56 +02:00
Martin Povišer	49906be776	select: Introduce `-assert-mod-count`	2024-05-21 16:34:38 +02:00
Martin Povišer	adc1a01490	select: Refactor some flag validation	2024-05-21 16:29:20 +02:00
Martin Povišer	c0a196173a	Rename `bbox_derive` to `box_derive`	2024-05-21 16:18:03 +02:00
N. Engelhardt	e940d248c0	Merge pull request #4326 from povik/logcmd ... Extend `log` command with `-push`, `-pop`, `-header` options	2024-05-21 15:22:40 +02:00
Martin Povišer	5c929a91c2	bbox_derive: Write help	2024-05-21 14:57:37 +02:00
Martin Povišer	88af059fad	bbox_derive: Fix `done` base type confusion	2024-05-21 14:57:26 +02:00
Emil J. Tywoniak	44b0fdc2bf	bbox_derive: add assert and debug print	2024-05-03 20:43:01 +02:00
Emil J. Tywoniak	e8c58a5528	bbox_derive: fix unininitialized memory UB when run with no named args	2024-05-03 20:41:42 +02:00
Martin Povišer	4c000d3aba	Add new `bbox_derive` command for blackbox derivation	2024-05-03 20:39:11 +02:00
Emil J. Tywoniak	e939182e68	cellmatch: add comments	2024-05-03 16:42:41 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to `$cellmatch`	2024-05-03 16:42:41 +02:00
Martin Povišer	c0e68dcc4d	cellmatch: Add debug print	2024-05-03 16:42:41 +02:00
Martin Povišer	6a9858cdad	cellmatch: Delegate evaluation to `ConstEval`	2024-05-03 16:42:41 +02:00
Martin Povišer	86e1080f05	cellmatch: New pass	2024-05-03 16:42:41 +02:00
Martin Povišer	6ff4ecb2b4	techmap: Remove `techmap_chtype` from the result	2024-05-03 13:33:28 +02:00
Martin Povišer	fc82251105	techmap: Support dynamic cell types	2024-05-03 13:33:28 +02:00
N. Engelhardt	34d9a7451e	Merge pull request #4333 from YosysHQ/fix_hierarchy_generate ... fix hierarchy -generate mode handling of cells	2024-04-25 09:56:24 +02:00
KrystalDelusion	c3ae33da33	Merge pull request #4285 from YosysHQ/typo_fixup ... Typo fixing	2024-04-25 09:54:48 +12:00
Martin Povišer	171577f909	Merge pull request #4340 from gadfort/abc-lib-merge ... add support for using ABCs library merging when providing multiple liberty files	2024-04-17 22:01:20 +02:00
Jannis Harder	2bd889a59a	formalff -setundef: Fix handling for has_srst FFs ... The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to a copy and paste error. This would crash when `has_ce` was false and could incorrectly determine that an initial value is unused when `has_ce` and `has_srst` are both set.	2024-04-15 11:53:30 +02:00
Martin Povišer	b827b9862f	Merge pull request #4265 from povik/iattr_help ... memory_map: Explain `-iattr` better	2024-04-13 18:13:58 +02:00
Martin Povišer	4a8cdfabbb	Merge pull request #4169 from povik/clean-opt_clean-step2 ... opt_clean: Remove dead assertion	2024-04-13 18:12:40 +02:00
Peter Gadfort	a48825a604	add support for using ABCs library merging when providing multiple liberty files	2024-04-12 13:57:29 -04:00
N. Engelhardt	b87327d1b9	fix hierarchy -generate mode handling of cells	2024-04-12 13:38:33 +02:00
Emil J	c5912f4f95	Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning ... opt_demorgan: fix extra args warning	2024-04-10 12:49:14 +02:00
Martin Povišer	b00abe4a26	Extend `log` command with `-push`, `-pop`, `-header` options	2024-04-10 11:49:20 +02:00
Martin Povišer	47931f9050	Merge pull request #4295 from gadfort/add-ports-stat ... add port statistics to stat command	2024-04-08 11:12:02 +02:00
Emil J. Tywoniak	4bb3b099d2	opt_demorgan: fix extra args warning	2024-04-03 10:02:53 +02:00
N. Engelhardt	c98cdc2a42	Merge pull request #4184 from povik/check-loop-edges ... Use cell edges data in `check`, improve messages	2024-03-25 16:19:35 +01:00
Peter Gadfort	160e3e089a	add port statistics to stat command	2024-03-22 09:20:20 -04:00
Krystine Sherwin	3eeefd23e3	Typo fixup(s)	2024-03-18 11:09:23 +13:00
N. Engelhardt	e4f11eb0a0	Merge pull request #4228 from povik/synth-inject ... synth: Introduce `-extra-map` for amending techmap	2024-03-11 14:55:45 +01:00
Martin Povišer	206d894c56	check: Omit private wires in loop report	2024-03-11 10:45:36 +01:00
Martin Povišer	d01728aaa5	celledges: Register async FF paths	2024-03-11 10:45:36 +01:00
Martin Povišer	4fdcf388d3	check: Assert edges data is not out-of-bounds	2024-03-11 10:45:17 +01:00
Martin Povišer	b6112b3551	check: Consider read ports in loop detection	2024-03-11 10:45:17 +01:00
Martin Povišer	fa74d0bd1a	check: Use cell edges data in detecting combinational loops	2024-03-11 10:43:49 +01:00
Martin Povišer	c5ae74af34	check: Improve found loop logging ... Print the detected loop in-order, and include source location for each node, if available.	2024-03-11 10:43:49 +01:00
N. Engelhardt	d70113a909	Merge pull request #3972 from nakengelhardt/celledges_shift_ops ... celledges: support shift ops	2024-03-08 09:35:47 +01:00
Martin Povišer	158fbf881e	memory_map: Explain `-iattr` better	2024-03-06 15:15:37 +01:00
Jannis Harder	04ecabdd1f	Merge pull request #4222 from jix/pdr-X ... write_aiger: Include `$assert` and `$assume` cells in -ywmap output	2024-03-05 15:13:51 +01:00
Jannis Harder	d8cdc213a6	rename -witness: Bug fix and rename formal cells ... Rename formal cells in addition to witness signals. This is required to reliably track individual property states for the non-smtbmc flows. Also removes a misplced `break` which resulted in only partial witness renaming.	2024-03-04 16:53:03 +01:00
Jannis Harder	16f6386613	Merge pull request #4224 from povik/equiv_simple-fix ... equiv_simple: Take FFs into account for driver map	2024-03-04 15:53:34 +01:00
N. Engelhardt	6dc5da3ed9	Merge pull request #4232 from povik/mem-ui-fixes ... opt_mem, memory_*: Refuse to operate in presence of processes	2024-02-26 16:09:27 +01:00
Roland Coeurjoly	4a2fb18718	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
Roland Coeurjoly	033fa10307	We use CXX instead of LD for linking yosys-filterlib	2024-02-25 16:49:28 +01:00
Martin Povišer	030d639201	opt_mem, memory_*: Refuse to operate in presence of processes ... Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes.	2024-02-23 12:27:53 +01:00
Martin Povišer	975517b022	memory_memx: Fix log header	2024-02-23 12:27:10 +01:00
Martin Povišer	53ca7b48f8	techmap: Fix help message wording	2024-02-22 22:00:56 +01:00
Martin Povišer	4c96546717	equiv_simple: Take FFs into account for driver map ... This fixes an issue introduced in commit 26644ea due to which flip-flops are inadvertently ignored when building up driver map. The mentioned commit wasn't without functional change after all.	2024-02-21 12:05:52 +01:00
Austin Rovinski	03cadf6474	dfflibmap: use patmatch() from kernel/yosys.cc ... Replace OS matching functions with yosys kernel function Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-20 11:04:55 -05:00
Miodrag Milanović	bc8a3a5b18	Merge pull request #4219 from rovinski/master ... dfflibmap: Add a -dont_use flag to ignore cells	2024-02-20 12:43:44 +01:00
Miodrag Milanović	a3c81f4d62	Merge pull request #4216 from YosysHQ/show_href ... show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-19 20:50:53 +01:00
Austin Rovinski	5059bb1d4f	dfflibmap: force PathMatchSpecA on WIN32 ... Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or LPCWSTR argument. char* is only convertable to LPCSTR, so use that implementation Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 14:40:46 -05:00
Austin Rovinski	689feed012	dfflibmap: Add a -dont_use flag to ignore cells ... This is an alternative to setting the dont_use property in lib. This brings dfflibmap in parity with the abc pass for dont_use. Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 13:00:18 -05:00
Martin Povišer	db947e4c71	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch ... proc_rom: don't assert on big actionless switch.	2024-02-19 16:21:40 +01:00
N. Engelhardt	4b99db0b73	Merge pull request #4177 from povik/connect-extra_args ... connect: Do interpret selection arguments	2024-02-19 15:18:37 +01:00
N. Engelhardt	aebb7a0c4d	Merge pull request #4188 from povik/dlatch-bwmux ... proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-19 15:15:03 +01:00
Amelia Cuss	bf4a46ccb3	proc_rom: don't assert on big actionless switch. ... See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.	2024-02-18 01:33:28 +11:00
N. Engelhardt	61b3b9b58a	Merge pull request #4197 from QuantamHD/sequential_area ... stat: Add sequential area output to stat -liberty	2024-02-16 19:15:44 +01:00
Ethan Mahintorabi	b8a1009de9	Update passes/cmds/stat.cc ... Make reporting line more clear about the non cumulative area of sequential cells Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>	2024-02-16 07:44:09 -08:00
Ethan Mahintorabi	f0df0e3912	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-16 00:01:44 +00:00
Ethan Mahintorabi	2d8343d423	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-15 23:59:19 +00:00
Jannis Harder	bbdfcfdf30	clk2fflogic: Fix handling of $check cells ... Fixes a bug in the handling of the recently introduced $check cells. Both $check and $print cells in clk2fflogic are handled by the same code and the existing tests for that were only using $print cells. This missed a bug where the additional A signal of $check cells that is not present on $print cells was dropped due to a typo, rendering $check cells non-functional. Also updates the tests to explicitly cover both cell types such that they would have detected the now fixed bug.	2024-02-14 11:42:27 +01:00
Miodrag Milanovic	834276a2f7	show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-14 09:50:53 +01:00
Miodrag Milanović	edb95c69a9	Merge pull request #4084 from jix/scopeinfo ... $scopeinfo support	2024-02-12 09:51:22 +01:00
Ethan Mahintorabi	8566489d85	stat: Add sequential area output to stat -liberty ... Checks to see if a cell is of type ff in the liberty, and keeps track of an additional area value. ``` Chip area for module '\addr': 92.280720 Sequential area for module '\addr': 38.814720 ``` Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-09 23:51:00 +00:00
Miodrag Milanović	2f4c917dac	Merge pull request #4181 from povik/ci-cxxstd-fix ... ci: Fix CXXSTD typo	2024-02-08 18:55:47 +01:00
Martin Povišer	043f1e2bcb	opt_lut: Remove leftover `-dlogic` help	2024-02-08 17:49:44 +01:00
Martin Povišer	af1a5cfeb9	Address `SigBit`/`SigSpec` confusion issues under c++20	2024-02-08 17:48:36 +01:00
Martin Povišer	862f2fd705	proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-08 00:08:50 +01:00
Jannis Harder	bfd9cf63db	Ignore $scopeinfo in opt_merge	2024-02-06 17:51:29 +01:00
Jannis Harder	8902fc94b6	Suport $scopeinfo in flatten and opt_clean	2024-02-06 17:51:29 +01:00
Miodrag Milanović	269c50f90e	Merge pull request #4130 from jix/hierarchy-defer-notop ... hierarchy: Without a known top module, derive all deferred modules	2024-02-06 12:08:01 +01:00
Jannis Harder	0470cbb00d	hierarchy: Without a known top module, derive all deferred modules ... This fixes hierarchy when used with cell libraries that were loaded with -defer and also makes more of the hierarchy visible to the auto-top heuristic.	2024-02-06 10:31:40 +01:00
Claire Xen	1b73b5beb7	Merge pull request #4174 from YosysHQ/claire/overwrite ... Add API to overwrite existing pass from plugin	2024-02-05 23:49:24 +01:00
N. Engelhardt	f96e27ac14	Merge pull request #4123 from povik/clean-opt_clean ... opt_clean: Add commentary, remove dead code	2024-02-05 15:08:34 +01:00
Catherine	c7bf0e3b8f	Add new `$check` cell to represent assertions with a message.	2024-02-01 20:10:39 +01:00
Jannis Harder	e1a59ba80b	async2sync, clk2fflogic: Add support for $check and $print cells	2024-02-01 20:10:39 +01:00
Jannis Harder	6c4902313b	chformal: Support $check cells and add chformal -lower ... This adds support for `$check` cells in chformal and adds a `-lower` mode which converts `$check` cells into `$assert` etc. cells with a `$print` cell to output the `$check` message.	2024-02-01 20:10:39 +01:00
Martin Povišer	a84fa0a277	connect: Do interpret selection arguments ... Instead of silently ignoring what would ordinarily be the selection arguments to a pass, interpret those and mark the support in the help message.	2024-02-01 10:28:36 +01:00
Martin Povišer	6c4bc5aae5	Merge pull request #4165 from phsauter/shiftadd-offset-fix ... peepopt: handle offset too large in `shiftadd`	2024-01-31 13:47:39 +01:00
Philippe Sauter	cbdf9b2f9c	peepopt: handle empty src-attribute in shiftadd	2024-01-31 13:07:01 +01:00
Claire Xenia Wolf	4fa314c0bd	Add API to overwrite existing pass from plugin ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-01-30 17:51:11 +01:00
Philippe Sauter	7f8b6dd982	peepopt: delete unnecessary comment in shiftadd	2024-01-30 09:51:21 +01:00
Martin Povišer	23c9828d70	opt_clean: Remove dead branch	2024-01-29 11:26:44 +01:00
Martin Povišer	7afc0696e2	opt_clean: Assert an impossible path isn't taken	2024-01-29 11:26:44 +01:00
Martin Povišer	ec065186d3	opt_clean: Add commentary around wire cleaning, NFC	2024-01-29 11:26:44 +01:00
Philippe Sauter	68a9aa7c29	peepopt: handle offset too large in `shiftadd` ... If the offset is larger than the signal itself, meaning the signal is completely shifted out, it tried to extract a negative amount of bits from the old signal. This RTL pattern is suspicious since it is a complicated way of arriving at a constant value, so we warn the user.	2024-01-26 16:44:30 +01:00
Jannis Harder	7c818d30f7	sim: Bring $print trigger/sampling semantics in line with FFs	2024-01-25 16:21:03 +01:00
Catherine	3d9e44d182	hierarchy: keep display statements, like formal assertions.	2024-01-22 10:09:22 +00:00
Stephen Tong	b3e7390c0e	Fix typo in stat help	2024-01-21 16:32:05 -05:00
N. Engelhardt	e1f4c5c9cb	Merge pull request #4133 from YosysHQ/show_color_proc ... show: allow setting colors via selection on PROC boxes	2024-01-17 17:56:53 +01:00
Martin Povišer	6a7fad4dd9	Merge pull request #4132 from povik/opt_lut_ice40 ... opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-17 14:26:28 +01:00
N. Engelhardt	fb4eeb1344	show: allow setting colors via selection on PROC boxes	2024-01-15 17:47:59 +01:00
Martin Povišer	149bcd88ad	Merge pull request #4026 from uis246/fix-format ... Fix printf formats	2024-01-15 16:04:11 +01:00
Martin Povišer	568418b50b	opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-15 12:35:21 +01:00
uis	5902b2826d	Fix printf formats	2024-01-15 12:07:54 +01:00
Dag Lem	acf916f654	Restore sim output from initial $display	2024-01-14 16:52:51 +01:00
Jannis Harder	57b4e16acd	sim: Include $display output in JSON summary ... This allows tools like SBY to capture the $display output independent from anything else sim might log. Additionally it provides source and hierarchy locations for everything printed.	2024-01-11 12:01:39 +01:00
N. Engelhardt	78541be4d8	Merge pull request #3971 from povik/equiv_simple-fixes ... Fixes to `equiv_simple`	2023-12-18 16:31:02 +01:00
Jannis Harder	cca12d9d9b	Merge pull request #4055 from povik/sim-hier-prints ... sim: Print hierarchy for failed assertions	2023-12-11 16:55:36 +01:00
Jannis Harder	7b74caa5db	peepopt: Fix padding for the peepopt_shiftmul_right pattern ... The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056	2023-12-06 18:35:44 +01:00
Martin Povišer	6581b5593c	sim: Print hierarchy for failed assertions	2023-12-06 12:09:07 +01:00
Martin Povišer	16ea497d7c	pmgen: Have a single make pattern ... Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode the other, and in some conditions there were build races as to whether the target directory for the generated header would exist. Instead have a single rule which is properly generalized.	2023-12-05 18:30:13 +01:00
Martin Povišer	d6566eb344	booth: Redo baseline architecture summation ... Redo the summation logic: strive for some degree of balance on the generated Wallace tree, emit an `$add` cell for the final summation.	2023-11-22 15:47:11 +01:00
Martin Povišer	beb5cb55a5	booth: Expose `-lowpower` option	2023-11-22 15:29:59 +01:00
Martin Povišer	7005ea9411	booth: Revisit help	2023-11-22 15:29:59 +01:00
Martin Povišer	48b73be8c6	booth: Replace the default signed architecture ... Generalize what was formerly the unsigned-only architecture to support both signed and unsigned multiplication, use that as default, and set aside the special low-power architecture that was formerly used for signed multipliers.	2023-11-22 15:29:59 +01:00
Martin Povišer	f50894d8bf	booth: Drop extra decoder arguments	2023-11-22 15:29:54 +01:00
Martin Povišer	579f6bdc17	booth: Do not special-case bottom rows ... Later on all the rows are cropped to the target size anyway, so there's no harm in transitionally including extra top bits.	2023-11-22 15:12:15 +01:00
Martin Povišer	da207cdce0	booth: Make less assumptions when aligning partial products	2023-11-22 15:12:15 +01:00
Martin Povišer	69e994ff75	booth: Clean unused FA index variable	2023-11-22 12:47:09 +01:00
Martin Povišer	d8408b2350	booth: Move up signed quadrant 1 logic	2023-11-22 12:46:15 +01:00
Martin Povišer	8d33cc2fb6	booth: Refactor signed CPA	2023-11-22 12:46:15 +01:00
Martin Povišer	00e899f98d	booth: Refactor signed multiplier full adders emission	2023-11-22 12:46:15 +01:00
N. Engelhardt	63cec22a0c	Merge pull request #3883 from phsauter/peepopt-shiftadd ... peepopt: Add `shiftadd` pattern	2023-11-07 10:42:15 +01:00
phsauter	3618294bac	peepopt: Add assert of consistent `shiftadd` data	2023-11-06 16:35:00 +01:00
Philippe Sauter	b6df900bcc	peepopt: Describe `shiftadd` rule in help message	2023-11-06 14:01:37 +01:00
phsauter	9ca57d9f13	peepopt: fix and refactor `shiftadd` ... - moved all selection and filtering logic to the match block - applied less-verbose code suggestions - removed constraint on number of bits in shift-amount - added check for possible wrap-arround in the operation	2023-11-06 14:01:37 +01:00
Philippe Sauter	72c6a01e67	peepopt: Add initial `shiftadd` pattern	2023-11-06 14:01:37 +01:00
N. Engelhardt	080da693d1	memory_libmap: update search order for attributes	2023-10-24 13:55:45 +02:00
N. Engelhardt	1b6d1e9419	memory_libmap: look for ram_style attributes on surrounding signals	2023-10-19 19:23:35 +02:00
Lofty	d21c464ae4	Merge pull request #3946 from rmlarsen/toposort ... Speed up TopoSort by 2.7-3.3x.	2023-10-17 13:00:18 +01:00
Claire Xen	a4951a3a97	Merge pull request #3986 from povik/sim-ui-fixes ... Slightly improve `sim` UI	2023-10-16 16:54:05 +02:00
N. Engelhardt	a2f59cf911	Merge pull request #3990 from zeldin/deterministic_scc	2023-10-16 16:51:54 +02:00
Martin Povišer	d6d1cc705e	pmgen: Fix sample syntax	2023-10-16 14:19:15 +02:00
Martin Povišer	660be4a31e	peepopt: Describe rules in help message	2023-10-16 14:19:15 +02:00
Martin Povišer	5c0c8251c3	peepopt: Remove broken `-generate` option	2023-10-16 14:19:10 +02:00
Martin Povišer	aa9b86aeec	peepopt: Add left-shift 'shiftmul' variant ... Add a separate shiftmul pattern to match on left shifts which implement demuxing. This mirrors the right shift pattern matcher but is probably best kept separate instead of merging the two into a single matcher. In any case the diff of the two matchers should be easily readable.	2023-10-16 13:52:38 +02:00
Martin Povišer	038a5e1ed4	peepopt: Support shift amounts zero-padded from below ... The `opt_expr` pass running before `peepopt` can interfere with the detection of a shiftmul pattern due to some of the bottom bits of the shift amount being replaced with constant zero. Extend the detection to cover those situations as well.	2023-10-16 13:52:06 +02:00
Martin Povišer	dd1a8ae49a	peepopt: Try to use original wires	2023-10-16 13:52:06 +02:00
Martin Povišer	bd8a81a907	peepopt: Clean up 'shiftmul' a bit ... No functional change intended.	2023-10-16 13:52:06 +02:00
Martin Povišer	a0c3be3aae	peepopt: Drop unused 'initbits' code ... Drop code that was once used by the 'dffmux' pattern but now is unused after that pattern has been obsoleted by the 'opt_dff' pass.	2023-10-16 13:52:06 +02:00
N. Engelhardt	6c562c76bc	fix handling right shifts	2023-10-12 11:46:09 +02:00
N. Engelhardt	3e22791810	Merge pull request #3975 from rmlarsen/optmerge	2023-10-09 17:05:19 +02:00
Marcus Comstedt	0ca39e233b	scc: Use hashlib instead of STL for deterministic behaviour	2023-10-07 10:43:00 +02:00
Rasmus Munk Larsen	0a37c2a301	Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. ... Add back statement that inserts nodes in order in opt_expr.cc.	2023-10-05 17:01:42 -07:00
Martin Povišer	c3fd88624a	sim: Bail on processes ... Instead of silently missimulating, error out when there are processes found in the simulation hierarchy.	2023-10-05 19:25:17 +02:00