2019-07-15 16:46:31 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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2019-09-09 22:58:54 -05:00
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static Cell* addDsp(Module *module) {
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Cell *cell = module->addCell(NEW_ID, "\\DSP48E1");
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cell->setParam("\\ACASCREG", 0);
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cell->setParam("\\ADREG", 0);
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cell->setParam("\\A_INPUT", Const("DIRECT"));
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cell->setParam("\\ALUMODEREG", 0);
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cell->setParam("\\AREG", 0);
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cell->setParam("\\BCASCREG", 0);
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cell->setParam("\\B_INPUT", Const("DIRECT"));
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cell->setParam("\\BREG", 0);
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cell->setParam("\\CARRYINREG", 0);
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cell->setParam("\\CARRYINSELREG", 0);
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cell->setParam("\\CREG", 0);
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cell->setParam("\\DREG", 0);
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cell->setParam("\\INMODEREG", 0);
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cell->setParam("\\MREG", 0);
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cell->setParam("\\OPMODEREG", 0);
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cell->setParam("\\PREG", 0);
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cell->setParam("\\USE_MULT", Const("NONE"));
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cell->setPort("\\D", Const(0, 24));
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cell->setPort("\\INMODE", Const(0, 5));
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cell->setPort("\\ALUMODE", Const(0, 4));
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cell->setPort("\\OPMODE", Const(0, 7));
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cell->setPort("\\CARRYINSEL", Const(0, 3));
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cell->setPort("\\ACIN", Const(0, 30));
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cell->setPort("\\BCIN", Const(0, 18));
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cell->setPort("\\PCIN", Const(0, 48));
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cell->setPort("\\CARRYIN", Const(0, 1));
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return cell;
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}
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2019-09-09 22:57:20 -05:00
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void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
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{
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2019-09-09 23:39:42 -05:00
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std::deque<Cell*> simd12_add, simd12_sub;
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std::deque<Cell*> simd24_add, simd24_sub;
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2019-09-09 22:57:20 -05:00
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for (auto cell : selected_cells) {
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2019-09-09 23:39:42 -05:00
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if (!cell->type.in("$add", "$sub"))
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2019-09-09 22:57:20 -05:00
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continue;
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SigSpec Y = cell->getPort("\\Y");
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if (!Y.is_chunk())
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continue;
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if (!Y.as_chunk().wire->get_strpool_attribute("\\use_dsp").count("simd"))
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continue;
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if (GetSize(Y) > 25)
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continue;
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SigSpec A = cell->getPort("\\A");
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SigSpec B = cell->getPort("\\B");
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if (GetSize(Y) <= 13) {
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if (GetSize(A) > 12)
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continue;
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if (GetSize(B) > 12)
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continue;
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2019-09-09 23:39:42 -05:00
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if (cell->type == "$add")
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simd12_add.push_back(cell);
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else if (cell->type == "$sub")
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simd12_sub.push_back(cell);
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2019-09-09 22:57:20 -05:00
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}
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2019-09-09 23:11:41 -05:00
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else if (GetSize(Y) <= 25) {
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2019-09-09 22:57:20 -05:00
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if (GetSize(A) > 24)
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continue;
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if (GetSize(B) > 24)
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continue;
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2019-09-09 23:39:42 -05:00
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if (cell->type == "$add")
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simd24_add.push_back(cell);
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else if (cell->type == "$sub")
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simd24_sub.push_back(cell);
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2019-09-09 22:57:20 -05:00
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}
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2019-09-09 23:11:41 -05:00
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else
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log_abort();
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2019-09-09 22:57:20 -05:00
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}
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2019-09-09 23:39:42 -05:00
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auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
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2019-09-09 22:57:20 -05:00
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SigSpec A = lane->getPort("\\A");
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SigSpec B = lane->getPort("\\B");
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SigSpec Y = lane->getPort("\\Y");
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A.extend_u0(12, lane->getParam("\\A_SIGNED").as_bool());
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B.extend_u0(12, lane->getParam("\\B_SIGNED").as_bool());
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AB.append(A);
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C.append(B);
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if (GetSize(Y) < 13)
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Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
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else
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log_assert(GetSize(Y) == 13);
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P.append(Y.extract(0, 12));
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CARRYOUT.append(Y[12]);
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};
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2019-09-09 23:39:42 -05:00
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auto g12 = [&f12,module](std::deque<Cell*> &simd12) {
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while (simd12.size() > 1) {
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SigSpec AB, C, P, CARRYOUT;
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2019-09-09 22:57:20 -05:00
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2019-09-09 23:39:42 -05:00
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Cell *lane1 = simd12.front();
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simd12.pop_front();
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Cell *lane2 = simd12.front();
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2019-09-09 22:57:20 -05:00
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simd12.pop_front();
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2019-09-09 23:39:42 -05:00
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Cell *lane3 = nullptr;
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Cell *lane4 = nullptr;
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2019-09-09 22:57:20 -05:00
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if (!simd12.empty()) {
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2019-09-09 23:39:42 -05:00
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lane3 = simd12.front();
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2019-09-09 22:57:20 -05:00
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simd12.pop_front();
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2019-09-09 23:39:42 -05:00
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if (!simd12.empty()) {
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lane4 = simd12.front();
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simd12.pop_front();
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}
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2019-09-09 22:57:20 -05:00
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}
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2019-09-09 23:39:42 -05:00
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log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
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2019-09-09 22:57:20 -05:00
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2019-09-09 23:39:42 -05:00
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Cell *cell = addDsp(module);
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cell->setParam("\\USE_SIMD", Const("FOUR12"));
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// X = A:B
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// Y = 0
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// Z = C
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cell->setPort("\\OPMODE", Const::from_string("0110011"));
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2019-09-09 22:57:20 -05:00
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2019-09-09 23:39:42 -05:00
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log_assert(lane1);
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log_assert(lane2);
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f12(AB, C, P, CARRYOUT, lane1);
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f12(AB, C, P, CARRYOUT, lane2);
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if (lane3) {
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f12(AB, C, P, CARRYOUT, lane3);
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if (lane4)
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f12(AB, C, P, CARRYOUT, lane4);
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else {
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AB.append(Const(0, 12));
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C.append(Const(0, 12));
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P.append(module->addWire(NEW_ID, 12));
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CARRYOUT.append(module->addWire(NEW_ID, 1));
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}
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}
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2019-09-09 22:57:20 -05:00
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else {
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2019-09-09 23:39:42 -05:00
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AB.append(Const(0, 24));
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C.append(Const(0, 24));
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P.append(module->addWire(NEW_ID, 24));
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CARRYOUT.append(module->addWire(NEW_ID, 2));
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2019-09-09 22:57:20 -05:00
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}
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2019-09-09 23:39:42 -05:00
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log_assert(GetSize(AB) == 48);
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log_assert(GetSize(C) == 48);
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log_assert(GetSize(P) == 48);
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log_assert(GetSize(CARRYOUT) == 4);
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cell->setPort("\\A", AB.extract(18, 30));
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cell->setPort("\\B", AB.extract(0, 18));
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cell->setPort("\\C", C);
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cell->setPort("\\P", P);
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cell->setPort("\\CARRYOUT", CARRYOUT);
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if (lane1->type == "$sub")
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cell->setPort("\\ALUMODE", Const::from_string("0011"));
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2019-09-09 22:57:20 -05:00
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2019-09-09 23:39:42 -05:00
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module->remove(lane1);
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module->remove(lane2);
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if (lane3) module->remove(lane3);
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if (lane4) module->remove(lane4);
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2019-09-09 22:57:20 -05:00
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2019-09-09 23:39:42 -05:00
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module->design->select(module, cell);
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}
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};
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g12(simd12_add);
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g12(simd12_sub);
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
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2019-09-09 23:11:41 -05:00
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SigSpec A = lane->getPort("\\A");
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SigSpec B = lane->getPort("\\B");
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SigSpec Y = lane->getPort("\\Y");
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A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool());
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B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool());
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2019-09-10 00:06:23 -05:00
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C.append(A);
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2019-09-09 23:39:42 -05:00
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AB.append(B);
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2019-09-09 23:11:41 -05:00
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if (GetSize(Y) < 25)
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Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
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else
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log_assert(GetSize(Y) == 25);
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P.append(Y.extract(0, 24));
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CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit
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CARRYOUT.append(Y[24]);
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};
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2019-09-09 23:39:42 -05:00
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auto g24 = [&f24,module](std::deque<Cell*> &simd24) {
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while (simd24.size() > 1) {
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SigSpec AB;
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SigSpec C;
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SigSpec P;
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SigSpec CARRYOUT;
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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Cell *lane1 = simd24.front();
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simd24.pop_front();
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Cell *lane2 = simd24.front();
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simd24.pop_front();
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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log("Analysing %s.%s for Xilinx DSP SIMD24 packing.\n", log_id(module), log_id(lane1));
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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Cell *cell = addDsp(module);
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cell->setParam("\\USE_SIMD", Const("TWO24"));
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// X = A:B
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// Y = 0
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// Z = C
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cell->setPort("\\OPMODE", Const::from_string("0110011"));
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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log_assert(lane1);
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log_assert(lane2);
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f24(AB, C, P, CARRYOUT, lane1);
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f24(AB, C, P, CARRYOUT, lane2);
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log_assert(GetSize(AB) == 48);
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log_assert(GetSize(C) == 48);
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log_assert(GetSize(P) == 48);
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log_assert(GetSize(CARRYOUT) == 4);
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cell->setPort("\\A", AB.extract(18, 30));
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cell->setPort("\\B", AB.extract(0, 18));
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cell->setPort("\\C", C);
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cell->setPort("\\P", P);
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cell->setPort("\\CARRYOUT", CARRYOUT);
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if (lane1->type == "$sub")
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cell->setPort("\\ALUMODE", Const::from_string("0011"));
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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module->remove(lane1);
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module->remove(lane2);
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2019-09-09 23:11:41 -05:00
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2019-09-09 23:39:42 -05:00
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module->design->select(module, cell);
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}
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};
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g24(simd24_add);
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g24(simd24_sub);
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2019-09-09 22:57:20 -05:00
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}
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2019-08-13 19:11:35 -05:00
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void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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2019-07-15 16:46:31 -05:00
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{
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auto &st = pm.st_xilinx_dsp;
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2019-07-16 16:06:32 -05:00
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#if 1
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2019-07-15 16:46:31 -05:00
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log("\n");
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2019-09-06 16:06:57 -05:00
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log("preAdd: %s\n", log_id(st.preAdd, "--"));
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2019-09-11 12:15:19 -05:00
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log("ffAD: %s %s %s\n", log_id(st.ffAD, "--"), log_id(st.ffADcemux, "--"), log_id(st.ffADrstmux, "--"));
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
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log("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
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log("ffD: %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
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2019-09-03 18:24:59 -05:00
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log("dsp: %s\n", log_id(st.dsp, "--"));
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2019-09-11 12:15:19 -05:00
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log("ffM: %s %s %s\n", log_id(st.ffM, "--"), log_id(st.ffMcemux, "--"), log_id(st.ffMrstmux, "--"));
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2019-09-03 18:24:59 -05:00
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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2019-09-11 12:15:19 -05:00
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log("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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2019-07-15 16:46:31 -05:00
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#endif
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2019-08-09 17:19:33 -05:00
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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2019-07-15 16:46:31 -05:00
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2019-07-16 16:06:32 -05:00
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Cell *cell = st.dsp;
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2019-08-13 19:11:35 -05:00
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bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
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2019-08-09 17:19:33 -05:00
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SigSpec P = st.sigP;
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2019-09-06 16:06:57 -05:00
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if (st.preAdd) {
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|
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
|
|
|
|
bool A_SIGNED = st.preAdd->getParam("\\A_SIGNED").as_bool();
|
|
|
|
bool D_SIGNED = st.preAdd->getParam("\\B_SIGNED").as_bool();
|
|
|
|
if (st.sigA == st.preAdd->getPort("\\B"))
|
|
|
|
std::swap(A_SIGNED, D_SIGNED);
|
|
|
|
st.sigA.extend_u0(30, A_SIGNED);
|
|
|
|
st.sigD.extend_u0(25, D_SIGNED);
|
|
|
|
cell->setPort("\\A", st.sigA);
|
|
|
|
cell->setPort("\\D", st.sigD);
|
|
|
|
cell->connections_.at("\\INMODE") = Const::from_string("00100");
|
|
|
|
|
|
|
|
if (st.ffAD) {
|
2019-09-11 12:15:19 -05:00
|
|
|
if (st.ffADcemux) {
|
|
|
|
SigSpec S = st.ffADcemux->getPort("\\S");
|
2019-09-10 20:59:03 -05:00
|
|
|
cell->setPort("\\CEAD", st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
|
2019-09-06 16:06:57 -05:00
|
|
|
}
|
|
|
|
else
|
|
|
|
cell->setPort("\\CEAD", State::S1);
|
|
|
|
cell->setParam("\\ADREG", 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
cell->setParam("\\USE_DPORT", Const("TRUE"));
|
|
|
|
|
|
|
|
pm.autoremove(st.preAdd);
|
|
|
|
}
|
2019-09-03 18:10:16 -05:00
|
|
|
if (st.postAdd) {
|
2019-09-06 16:06:57 -05:00
|
|
|
log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
|
2019-09-03 16:57:59 -05:00
|
|
|
|
|
|
|
SigSpec &opmode = cell->connections_.at("\\OPMODE");
|
2019-09-03 18:37:59 -05:00
|
|
|
if (st.postAddMux) {
|
|
|
|
log_assert(st.ffP);
|
2019-09-03 18:24:59 -05:00
|
|
|
opmode[4] = st.postAddMux->getPort("\\S");
|
|
|
|
pm.autoremove(st.postAddMux);
|
2019-09-03 17:53:10 -05:00
|
|
|
}
|
2019-09-06 23:01:36 -05:00
|
|
|
else if (st.ffP && st.sigC == P)
|
2019-09-03 16:57:59 -05:00
|
|
|
opmode[4] = State::S0;
|
|
|
|
else
|
|
|
|
opmode[4] = State::S1;
|
|
|
|
opmode[6] = State::S0;
|
|
|
|
opmode[5] = State::S1;
|
|
|
|
|
2019-09-06 23:01:36 -05:00
|
|
|
if (opmode[4] != State::S0) {
|
|
|
|
if (st.postAddMuxAB == "\\A")
|
|
|
|
st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
|
|
|
|
else
|
|
|
|
st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
|
|
|
|
cell->setPort("\\C", st.sigC);
|
|
|
|
}
|
|
|
|
|
2019-09-03 18:10:16 -05:00
|
|
|
pm.autoremove(st.postAdd);
|
2019-09-03 16:57:59 -05:00
|
|
|
}
|
|
|
|
|
2019-07-15 16:46:31 -05:00
|
|
|
if (st.clock != SigBit())
|
|
|
|
{
|
|
|
|
cell->setPort("\\CLK", st.clock);
|
|
|
|
|
2019-09-11 12:15:19 -05:00
|
|
|
auto f = [&pm,cell](IdString port, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
|
|
|
|
SigSpec A = cell->getPort(port);
|
|
|
|
SigSpec D = ff->getPort("\\D");
|
|
|
|
SigSpec Q = pm.sigmap(ff->getPort("\\Q"));
|
2019-07-17 14:45:25 -05:00
|
|
|
A.replace(Q, D);
|
2019-09-11 12:15:19 -05:00
|
|
|
if (rstmux) {
|
|
|
|
SigSpec Y = rstmux->getPort("\\Y");
|
|
|
|
SigSpec AB = rstmux->getPort(rstpol ? "\\A" : "\\B");
|
|
|
|
SigSpec S = rstmux->getPort("\\S");
|
2019-09-05 23:38:35 -05:00
|
|
|
A.replace(Y, AB);
|
2019-09-11 12:15:19 -05:00
|
|
|
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
cell->setPort(rstport, State::S0);
|
|
|
|
if (cemux) {
|
|
|
|
SigSpec Y = cemux->getPort("\\Y");
|
|
|
|
SigSpec BA = cemux->getPort(cepol ? "\\B" : "\\A");
|
|
|
|
SigSpec S = cemux->getPort("\\S");
|
|
|
|
A.replace(Y, BA);
|
|
|
|
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
|
2019-09-05 12:07:26 -05:00
|
|
|
}
|
|
|
|
else
|
2019-09-11 12:15:19 -05:00
|
|
|
cell->setPort(ceport, State::S1);
|
|
|
|
cell->setPort(port, A);
|
|
|
|
};
|
2019-09-05 12:46:33 -05:00
|
|
|
|
2019-09-11 12:15:19 -05:00
|
|
|
if (st.ffA) {
|
|
|
|
f("\\A", st.ffA, st.ffAcemux, st.ffAcepol, "\\CEA2", st.ffArstmux, st.ffArstpol, "\\RSTA");
|
2019-09-05 12:46:33 -05:00
|
|
|
cell->setParam("\\AREG", 1);
|
2019-07-15 16:46:31 -05:00
|
|
|
}
|
|
|
|
if (st.ffB) {
|
2019-09-11 12:15:19 -05:00
|
|
|
f("\\B", st.ffB, st.ffBcemux, st.ffBcepol, "\\CEB2", st.ffBrstmux, st.ffBrstpol, "\\RSTB");
|
2019-08-08 12:44:49 -05:00
|
|
|
cell->setParam("\\BREG", 1);
|
2019-07-15 16:46:31 -05:00
|
|
|
}
|
2019-09-06 23:01:36 -05:00
|
|
|
if (st.ffC) {
|
2019-09-11 12:15:19 -05:00
|
|
|
f("\\C", st.ffC, st.ffCcemux, st.ffCcepol, "\\CEC", st.ffCrstmux, st.ffCrstpol, "\\RSTC");
|
2019-09-06 23:01:36 -05:00
|
|
|
cell->setParam("\\CREG", 1);
|
|
|
|
}
|
2019-09-06 17:32:26 -05:00
|
|
|
if (st.ffD) {
|
2019-09-11 12:15:19 -05:00
|
|
|
f("\\D", st.ffD, st.ffDcemux, st.ffDcepol, "\\CED", st.ffDrstmux, st.ffDrstpol, "\\RSTD");
|
2019-09-06 17:32:26 -05:00
|
|
|
cell->setParam("\\DREG", 1);
|
|
|
|
}
|
2019-08-30 17:00:56 -05:00
|
|
|
if (st.ffM) {
|
2019-09-11 09:34:14 -05:00
|
|
|
if (st.ffMrstmux) {
|
|
|
|
SigSpec S = st.ffMrstmux->getPort("\\S");
|
|
|
|
cell->setPort("\\RSTM", st.ffMrstpol ? S : pm.module->Not(NEW_ID, S));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
cell->setPort("\\RSTM", State::S0);
|
|
|
|
if (st.ffMcemux) {
|
|
|
|
SigSpec S = st.ffMcemux->getPort("\\S");
|
2019-09-10 20:59:03 -05:00
|
|
|
cell->setPort("\\CEM", st.ffMcepol ? S : pm.module->Not(NEW_ID, S));
|
2019-09-04 12:52:51 -05:00
|
|
|
}
|
|
|
|
else
|
2019-08-30 17:00:56 -05:00
|
|
|
cell->setPort("\\CEM", State::S1);
|
2019-09-05 13:00:27 -05:00
|
|
|
SigSpec D = st.ffM->getPort("\\D");
|
|
|
|
SigSpec Q = st.ffM->getPort("\\Q");
|
2019-09-11 09:34:14 -05:00
|
|
|
st.ffM->connections_.at("\\Q").replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
|
|
|
|
|
|
|
|
for (auto c : Q.chunks()) {
|
|
|
|
auto it = c.wire->attributes.find("\\init");
|
|
|
|
if (it == c.wire->attributes.end())
|
|
|
|
continue;
|
|
|
|
for (int i = c.offset; i < c.offset+c.width; i++) {
|
|
|
|
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
|
|
|
|
it->second[i] = State::Sx;
|
|
|
|
}
|
|
|
|
}
|
2019-09-05 13:00:27 -05:00
|
|
|
|
|
|
|
cell->setParam("\\MREG", State::S1);
|
2019-08-30 17:00:56 -05:00
|
|
|
}
|
2019-07-16 16:06:32 -05:00
|
|
|
if (st.ffP) {
|
2019-09-10 22:51:48 -05:00
|
|
|
if (st.ffPrstmux) {
|
|
|
|
SigSpec S = st.ffPrstmux->getPort("\\S");
|
|
|
|
cell->setPort("\\RSTP", st.ffPrstpol ? S : pm.module->Not(NEW_ID, S));
|
|
|
|
}
|
|
|
|
else
|
2019-09-10 22:56:13 -05:00
|
|
|
cell->setPort("\\RSTP", State::S0);
|
2019-09-10 22:51:48 -05:00
|
|
|
if (st.ffPcemux) {
|
|
|
|
SigSpec S = st.ffPcemux->getPort("\\S");
|
2019-09-10 20:59:03 -05:00
|
|
|
cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));
|
2019-09-05 13:00:27 -05:00
|
|
|
}
|
|
|
|
else
|
2019-07-16 16:06:32 -05:00
|
|
|
cell->setPort("\\CEP", State::S1);
|
2019-09-05 13:00:27 -05:00
|
|
|
SigSpec Q = st.ffP->getPort("\\Q");
|
2019-08-01 17:10:43 -05:00
|
|
|
st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
|
2019-09-05 13:00:27 -05:00
|
|
|
|
2019-09-10 23:33:14 -05:00
|
|
|
for (auto c : Q.chunks()) {
|
|
|
|
auto it = c.wire->attributes.find("\\init");
|
|
|
|
if (it == c.wire->attributes.end())
|
|
|
|
continue;
|
|
|
|
for (int i = c.offset; i < c.offset+c.width; i++) {
|
|
|
|
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
|
|
|
|
it->second[i] = State::Sx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-05 13:00:27 -05:00
|
|
|
cell->setParam("\\PREG", State::S1);
|
2019-07-15 16:46:31 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
log(" clock: %s (%s)", log_signal(st.clock), "posedge");
|
|
|
|
|
|
|
|
if (st.ffA)
|
|
|
|
log(" ffA:%s", log_id(st.ffA));
|
|
|
|
|
2019-09-06 16:10:12 -05:00
|
|
|
if (st.ffAD)
|
|
|
|
log(" ffAD:%s", log_id(st.ffAD));
|
|
|
|
|
2019-07-15 16:46:31 -05:00
|
|
|
if (st.ffB)
|
|
|
|
log(" ffB:%s", log_id(st.ffB));
|
|
|
|
|
2019-09-06 23:01:36 -05:00
|
|
|
if (st.ffC)
|
|
|
|
log(" ffC:%s", log_id(st.ffC));
|
|
|
|
|
|
|
|
if (st.ffD)
|
|
|
|
log(" ffD:%s", log_id(st.ffD));
|
|
|
|
|
2019-09-05 13:46:38 -05:00
|
|
|
if (st.ffM)
|
|
|
|
log(" ffM:%s", log_id(st.ffM));
|
|
|
|
|
2019-07-16 16:06:32 -05:00
|
|
|
if (st.ffP)
|
2019-08-08 18:33:37 -05:00
|
|
|
log(" ffP:%s", log_id(st.ffP));
|
2019-07-15 16:46:31 -05:00
|
|
|
|
|
|
|
log("\n");
|
|
|
|
}
|
|
|
|
|
2019-08-09 17:19:33 -05:00
|
|
|
if (GetSize(P) < 48)
|
|
|
|
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
|
|
|
|
cell->setPort("\\P", P);
|
|
|
|
|
2019-07-16 16:06:32 -05:00
|
|
|
pm.blacklist(cell);
|
2019-07-15 16:46:31 -05:00
|
|
|
}
|
|
|
|
|
2019-08-13 12:23:07 -05:00
|
|
|
struct XilinxDspPass : public Pass {
|
2019-09-10 18:33:13 -05:00
|
|
|
XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { }
|
2019-07-15 16:46:31 -05:00
|
|
|
void help() YS_OVERRIDE
|
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
|
|
|
log(" xilinx_dsp [options] [selection]\n");
|
|
|
|
log("\n");
|
2019-09-11 12:15:19 -05:00
|
|
|
log("Pack input registers (A, B, C, D, AD; with optional enable/reset), pipeline\n");
|
|
|
|
log("registers (M; with optional enable/reset), output registers (P; with optional\n");
|
|
|
|
log("enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.\n");
|
2019-09-10 18:33:13 -05:00
|
|
|
log("\n");
|
|
|
|
log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
|
|
|
|
log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
|
|
|
|
log("used to override the existing accumulation result with a new value.\n");
|
|
|
|
log("\n");
|
2019-09-10 18:35:10 -05:00
|
|
|
log("Use of the dedicated 'PCOUT' -> 'PCIN' path is detected for 'P' -> 'C' connections\n");
|
|
|
|
log("where 'P' is right-shifted by 18-bits and used as an input to the post-adder (a\n");
|
|
|
|
log("pattern common for summing partial products to implement wide multiplies).\n");
|
2019-09-10 18:33:13 -05:00
|
|
|
log("\n");
|
|
|
|
log("\n");
|
|
|
|
log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
|
|
|
|
log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n");
|
|
|
|
log("the add/subtract operator will cause those operations to be implemented using\n");
|
|
|
|
log("the 'SIMD' feature of DSPs.\n");
|
2019-07-15 16:46:31 -05:00
|
|
|
log("\n");
|
|
|
|
}
|
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
|
|
{
|
2019-09-10 18:33:13 -05:00
|
|
|
log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n");
|
2019-07-15 16:46:31 -05:00
|
|
|
|
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
|
|
{
|
|
|
|
// if (args[argidx] == "-singleton") {
|
|
|
|
// singleton_mode = true;
|
|
|
|
// continue;
|
|
|
|
// }
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
2019-08-13 19:11:35 -05:00
|
|
|
for (auto module : design->selected_modules()) {
|
2019-09-09 22:57:20 -05:00
|
|
|
pack_xilinx_simd(module, module->selected_cells());
|
|
|
|
|
2019-08-13 19:11:35 -05:00
|
|
|
xilinx_dsp_pm pm(module, module->selected_cells());
|
|
|
|
dict<SigBit, Cell*> bit_to_driver;
|
|
|
|
auto f = [&bit_to_driver](xilinx_dsp_pm &pm){ pack_xilinx_dsp(bit_to_driver, pm); };
|
|
|
|
pm.run_xilinx_dsp(f);
|
|
|
|
|
|
|
|
// Look for ability to convert C input from another DSP into PCIN
|
|
|
|
// NB: Needs to be done after pattern matcher has folded all
|
|
|
|
// $add cells into the DSP
|
|
|
|
for (auto cell : module->cells()) {
|
|
|
|
if (cell->type != "\\DSP48E1")
|
|
|
|
continue;
|
2019-09-06 23:01:36 -05:00
|
|
|
if (cell->parameters.at("\\CREG", State::S1).as_bool())
|
|
|
|
continue;
|
2019-08-13 19:11:35 -05:00
|
|
|
SigSpec &opmode = cell->connections_.at("\\OPMODE");
|
|
|
|
if (opmode.extract(4,3) != Const::from_string("011"))
|
|
|
|
continue;
|
|
|
|
SigSpec C = pm.sigmap(cell->getPort("\\C"));
|
|
|
|
if (C.has_const())
|
|
|
|
continue;
|
|
|
|
auto it = bit_to_driver.find(C[0]);
|
|
|
|
if (it == bit_to_driver.end())
|
|
|
|
continue;
|
|
|
|
auto driver = it->second;
|
|
|
|
|
|
|
|
// Unextend C
|
|
|
|
int i;
|
|
|
|
for (i = GetSize(C)-1; i > 0; i--)
|
|
|
|
if (C[i] != C[i-1])
|
|
|
|
break;
|
|
|
|
if (i > 48-17)
|
|
|
|
continue;
|
|
|
|
if (driver->getPort("\\P").extract(17, i) == C.extract(0, i)) {
|
|
|
|
cell->setPort("\\C", Const(0, 48));
|
|
|
|
Wire *cascade = module->addWire(NEW_ID, 48);
|
|
|
|
driver->setPort("\\PCOUT", cascade);
|
|
|
|
cell->setPort("\\PCIN", cascade);
|
|
|
|
opmode[6] = State::S1;
|
|
|
|
opmode[5] = State::S0;
|
|
|
|
opmode[4] = State::S1;
|
|
|
|
bit_to_driver.erase(it);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-07-15 16:46:31 -05:00
|
|
|
}
|
2019-08-13 12:23:07 -05:00
|
|
|
} XilinxDspPass;
|
2019-07-15 16:46:31 -05:00
|
|
|
|
|
|
|
PRIVATE_NAMESPACE_END
|