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caravel
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626 Commits 141 Branches 61 Tags 15 GiB
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41 Commits

Author SHA1 Message Date
M0stafaRady 3fe7f3f38b fix tests timeout 2022-10-11 06:04:16 -07:00
M0stafaRady 7fe790649d Add gpio_all_bidir_user test 2022-10-10 15:59:20 -07:00
M0stafaRady 8cca3a5002 Add gpio_all_i_pd_user and gpio_all_i_pu_user 2022-10-10 14:49:24 -07:00
M0stafaRady a572a8ec14 add gpio_all_i_user test 2022-10-10 09:07:32 -07:00
M0stafaRady e2245ad333 enhance gpio_all_i test to include more checkers 2022-10-10 07:42:02 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
M0stafaRady 1690c8e068 enhance gpio_all_o test 2022-10-09 06:07:19 -07:00
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00
M0stafaRady d90001eac2 update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
M0stafaRady 0f167fc041 update timeout for gpio_all_i_pd and gpio_all_i_pu 2022-10-07 07:02:09 -07:00
M0stafaRady f072e9cb2d Add gpio_all_i_pd 2022-10-07 06:41:21 -07:00
M0stafaRady e1eba1d534 update gpio_all_i_pu test 2022-10-07 06:04:18 -07:00
M0stafaRady 4f483adb36 update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
M0stafaRady 7e407e1155 Add test hk_disable 2022-10-06 10:12:12 -07:00
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
M0stafaRady fb34d9a541 update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
M0stafaRady 8e72d5e13e Add test uart_loopback 2022-10-06 03:12:44 -07:00
M0stafaRady 6830c79ae8 fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
M0stafaRady a6e7b46128 delete reading from uart register in uart_rx test 2022-10-05 15:07:38 -07:00
M0stafaRady 78613c95cc increase timeout for uart_rx and add uart_ev_pending_write 2022-10-05 15:02:07 -07:00
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
M0stafaRady 4610f6b004 Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
M0stafaRady e2b345dcbb Add new test user_pass_thru_rd 2022-10-04 10:55:53 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
M0stafaRady ef9c2e408b fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
M0stafaRady e81416bb51 add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
M0stafaRady e945c3b882 fix bug at mgmt_gpio_out by increasing the number of phases 2022-10-03 05:45:55 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
M0stafaRady cb929cb329 Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00