Commit Graph

421 Commits

Author SHA1 Message Date
M0stafaRady 927c216a6b Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:38:32 -07:00
M0stafaRady 752d12928b fix iverlog command for the new structure 2022-10-02 06:38:22 -07:00
M0stafaRady d8a4b812e8 update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode 2022-10-02 06:37:12 -07:00
M0stafaRady 00a029fec3
Update README.md 2022-10-02 15:17:21 +02:00
M0stafaRady bf9b363f68
Update README.md 2022-10-02 15:01:15 +02:00
M0stafaRady 32607cc118 delete uart_rx hex 2022-10-02 05:40:44 -07:00
M0stafaRady b045977af0 merge with remote branch 2022-10-02 05:39:23 -07:00
M0stafaRady cb929cb329 Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
M0stafaRady bc9eb2eb31
Update README.md 2022-10-02 14:35:49 +02:00
M0stafaRady 928fc6a2a5
Update README.md 2022-10-02 14:27:42 +02:00
M0stafaRady a0da0fc906
add photo of cocotb structure 2022-10-02 14:10:17 +02:00
M0stafaRady ad053568e7
Create README.md
add READme in doc file
2022-10-02 14:09:49 +02:00
M0stafaRady bd712f64d4 rename cocotb.py to verify_cocotb.py 2022-10-02 04:29:48 -07:00
M0stafaRady b5fb97e5f4 rename run.py to cocotb.py 2022-10-02 04:22:44 -07:00
M0stafaRady 9e0be5473d remove hex files from directory 2022-10-02 04:20:32 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 199d5c0f5c fix bug assert csb before reset for the GL sim to work 2022-10-01 12:36:02 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00
M0stafaRady f2ca45358b remove AN.DB folder from git hub 2022-09-30 03:52:34 -07:00
M0stafaRady 7546ce10c7 simple readme 2022-09-30 03:52:34 -07:00
M0stafaRady f08c22023c Apply automatic changes to Manifest and README.rst 2022-09-30 03:52:34 -07:00
M0stafaRady f8c8d831d0 Add RTL for 2 debug regs used to test and located inside user_project_wrapper 2022-09-30 03:52:34 -07:00
M0stafaRady fc8369443c fix bug move some housekeeping initialization wires and regs before they are used 2022-09-30 03:52:34 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
Marwan Abbas c9c7fc5533
Merge pull request #134 from efabless/fix_user_pass_thru
Fix user pass thru
2022-09-29 19:52:13 +02:00
kareem 7c524edd31 openlane(wip)!: housekeeping
~ fix typo in referencing variables in sdc file
~ fine tune parameters to get the design to route
with cts and diode insertion

!important:
depends on SAVE_LIB patch from openlane
2022-09-29 05:30:03 -07:00
Kareem Farid 0a56c1c4eb update housekeeping sdc 2022-09-29 12:54:28 +02:00
kareem 53950bb206 openlane: update gpio_control_block config
- point to the right template file
- add skiptrim flag
2022-09-28 01:03:00 -07:00
kareem acf92c3460 views: update gpio_control_block gds 2022-09-27 07:42:32 -07:00
kareem 85f7f86c4e reharden!: gpio_control_block
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
2022-09-27 07:09:26 -07:00
kareem c1e0d5ba06 openlane!: reharden gpio_control_block
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`

!IMPORTANT - still need to run dynamic simulations
2022-09-14 11:06:23 -07:00
Tim Edwards 1b4637dbb7 Merge branch 'main' into fix_serial_loader_data_timing
Merging latest changes from main branch into this fix.
2022-09-02 10:02:36 -04:00
sto6 9949306c42
issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110)
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.

Co-authored-by: Risto Bell <rb@efabless.com>
2022-08-26 23:03:00 -07:00
kareem ac1928a45b harden: gpio_control_block with updated rtl
TODO: run full verification
2022-08-15 02:29:01 -07:00
RTimothyEdwards 54901e267c Apply automatic changes to Manifest and README.rst 2022-07-24 20:21:58 +00:00
Tim Edwards e6030f9fb3 Modified the GPIO control block verilog to remove the delay stages
from the data and replace them with a single flop clocked on the
negative edge of the serial clock.  This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
2022-07-24 16:17:56 -04:00
Jeff DiCorpo 6a6d6a8c77
Update Makefile
Compress filter for oasis files in tapeout
2022-07-07 15:36:19 -07:00
RTimothyEdwards 485d9df7e3 Apply automatic changes to Manifest and README.rst 2022-06-07 14:46:03 +00:00
Tim Edwards 298ede362b Corrects an issue with the user pass-through flash programming
mode in which the data and clock are activated simultaneously,
so the first data bit after CSB goes low may or may not be
seen by the SPI flash.
2022-06-07 10:42:56 -04:00
matt venn 44a83f90eb
add links to litex core (#96)
and make it clear docs are split into 2
2022-05-08 22:52:47 -07:00
R. Timothy Edwards d882f42803
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90)
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
    3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
    make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
    xschem-generated schematic netlist.

NOTE: None of these modifications change the function of any circuit.  The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate.  This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled.  It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.

* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).

* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
2022-05-08 22:51:29 -07:00
R. Timothy Edwards a2ccbd9e7e
Modified the set_user_id.py script so that mode "-report" returns a valid value. (#93)
* Modified the set_user_id.py script so that mode "-report" returns
a valid value, instead of throwing an error, because the "info.yaml"
file was removed without due consideration of the side effects.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-05-08 22:50:48 -07:00
R. Timothy Edwards 80c7d29412
A minor correction the gen_gpio_defaults.py script to ensure that (#95)
it will recognize all block cell types in the gate level netlist
after having been run previously.  The former code was only looking
for numeric digits in the cell name, but the cell name suffix is
hex, not integer, and so the script needs to add a check for the
letters A-F or a-f in the cell name suffix.  This is not an
immediate issue because the two default values used are "0403" and
"1803" and happen not to have any alphabetic hex digits.  But if
it were deemed necessary to change a default, then this script
should not break.
2022-05-08 22:50:20 -07:00
Marwan Abbas 6cfedf89a2
fixed caravel netlist to use the 1803 defaults block (#94)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-05-03 10:36:11 -07:00