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openlane(wip)!: housekeeping 

~ fix typo in referencing variables in sdc file
~ fine tune parameters to get the design to route
with cts and diode insertion

!important:
depends on SAVE_LIB patch from openlane
This commit is contained in:
kareem 2022-09-29 05:30:03 -07:00
parent 0a56c1c4eb
commit 7c524edd31
2 changed files with 28 additions and 29 deletions
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10
openlane/housekeeping/base.sdc
View File

@ -36,10 +36,10 @@ puts "\[INFO\]: Setting input delay to: $input_delay_value"
## Filter clocks from the all inputs
set sck_clk_indx [lsearch [all_inputs] [get_port "mgmt_gpio_in[4]"]]
set all_inputs_wo_sckclk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
set wb_clk_indx [lsearch all_inputs_wo_sckclk [get_port "wb_clk_i"]]
set all_inputs_wo_2clks [lreplace all_inputs_wo_sckclk $wb_clk_indx $wb_clk_indx]
set usr_clk_indx [lsearch all_inputs_wo_2clks [get_port "user_clock"]]
set all_inputs_wo_clk [lreplace all_inputs_wo_2clks $usr_clk_indx $usr_clk_indx]
set wb_clk_indx [lsearch $all_inputs_wo_sckclk [get_port "wb_clk_i"]]
set all_inputs_wo_2clks [lreplace $all_inputs_wo_sckclk $wb_clk_indx $wb_clk_indx]
set usr_clk_indx [lsearch $all_inputs_wo_2clks [get_port "user_clock"]]
set all_inputs_wo_clk [lreplace $all_inputs_wo_2clks $usr_clk_indx $usr_clk_indx]
set_input_delay $input_delay_value -clock [get_clocks wb_clk_i] $all_inputs_wo_clk
@ -141,4 +141,4 @@ set_clock_transition $sck_clk_tran [get_clocks {sck}]
## FANOUT
set ::env(SYNTH_MAX_FANOUT) 7
puts "\[INFO\]: Setting maximum fanout to: $::env(SYNTH_MAX_FANOUT)"
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]

47
openlane/housekeeping/config.tcl
View File

@ -14,57 +14,56 @@
# SPDX-License-Identifier: Apache-2.0
# OR COMMIT: 182e733faa149c80f36cfd2198a83dcdeb7853ea
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) "housekeeping"
set ::env(ROUTING_CORES) 6
set ::env(ROUTING_CORES) 36
set ::env(RUN_KLAYOUT) 0
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/housekeeping_spi.v\
$script_dir/../../verilog/rtl/housekeeping.v"
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping_spi.v\
$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping.v"
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]"
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/housekeeping.def
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
## Synthesis
set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/no_synth.list
set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(SYNTH_MAX_FANOUT) 20
set ::env(SYNTH_MAX_FANOUT) 7
## Floorplan
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 300.230 550.950"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_IO_MIN_DISTANCE) 2
set ::env(CELL_PAD) 0
set ::env(DPL_CELL_PADDING) 2
set ::env(GPL_CELL_PADDING) 2
## Routing
set ::env(GLB_RT_ADJUSTMENT) 0.06
set ::env(GLB_RT_OVERFLOW_ITERS) 100
set ::env(GRT_ADJUSTMENT) 0.06
set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.2,0,0,0,0"
set ::env(GRT_OVERFLOW_ITERS) 100
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
# prevent signal routing on li1
set ::env(GLB_RT_OBS) "\
li1 0 0 5.94500 550.950,\
li1 0 0 300.23000 10.97000,\
li1 294.23500 0 300.22000 550.95000,\
li1 0 538.84500 300.2300 550.95000"
## Placement
set ::env(PL_TARGET_DENSITY) 0.378
set ::env(PL_TARGET_DENSITY) 0.5
set ::env(GRT_ALLOW_CONGESTION) 0
set ::env(CLOCK_TREE_SYNTH) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) .17
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
## Diode Insertion
set ::env(DIODE_INSERTION_STRATEGY) "3"
set ::env(GLB_RT_ANT_ITERS) "7"
set ::env(GRT_ANT_ITERS) "7"