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A minor correction the gen_gpio_defaults.py script to ensure that (#95) 

it will recognize all block cell types in the gate level netlist
after having been run previously.  The former code was only looking
for numeric digits in the cell name, but the cell name suffix is
hex, not integer, and so the script needs to add a check for the
letters A-F or a-f in the cell name suffix.  This is not an
immediate issue because the two default values used are "0403" and
"1803" and happen not to have any alphabetic hex digits.  But if
it were deemed necessary to change a default, then this script
should not break.
This commit is contained in:
R. Timothy Edwards 2022-05-09 01:50:20 -04:00 committed by GitHub
parent 6cfedf89a2
commit 80c7d29412
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1 changed files with 2 additions and 2 deletions
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scripts/gen_gpio_defaults.py
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@ -362,8 +362,8 @@ if __name__ == '__main__':
# Do the same to the top gate-level verilog
inst1rex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+.?gpio_defaults_block_([0-9]+).([0-9]+)')
inst2rex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+gpio_defaults_block_([0-9]+)')
inst1rex = re.compile('[ \t]*(gpio_defaults_block_?[0-1]?[0-9A-Fa-f]*)[ \t]+.?gpio_defaults_block_([0-9]+).([0-9]+)')
inst2rex = re.compile('[ \t]*(gpio_defaults_block_?[0-1]?[0-9A-Fa-f]*)[ \t]+gpio_defaults_block_([0-9]+)')
if testmode:
print('Test only: Caravel top gate-level verilog:')