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477 Commits

Author SHA1 Message Date
M0stafaRady 3eb0b11380 update verify_cocotb.py to remove vcs generate files 2022-10-06 11:18:48 -07:00
M0stafaRady 4f483adb36 update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
M0stafaRady 7e407e1155 Add test hk_disable 2022-10-06 10:12:12 -07:00
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
M0stafaRady fb34d9a541 update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
M0stafaRady a69185dfca update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00
M0stafaRady 1bc78c4eea update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:43:02 -07:00
M0stafaRady 8e72d5e13e Add test uart_loopback 2022-10-06 03:12:44 -07:00
M0stafaRady 6830c79ae8 fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
M0stafaRady a6e7b46128 delete reading from uart register in uart_rx test 2022-10-05 15:07:38 -07:00
M0stafaRady 78613c95cc increase timeout for uart_rx and add uart_ev_pending_write 2022-10-05 15:02:07 -07:00
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
M0stafaRady fca511f306 change docker mount from the home to repo directory and pdk root 2022-10-05 11:10:24 -07:00
M0stafaRady a741ec4525 Merge branch 'caravel_redesign' into cocotb 2022-10-05 08:24:30 -07:00
M0stafaRady 86373a55e3 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-05 08:23:17 -07:00
M0stafaRady 4610f6b004 Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
kareem aaa3b863e5 reharden!: gpio_control_clock 
- add met5 obs to avoid drc with the top level pdn

!important: still need to use the latest openlane to replicate
 2022-10-05 07:03:11 -07:00
Mohamed Shalan dc105c6796
Merge pull request #146 from efabless/mgmt_fix 
fix  typos in mgmt_protect.v
 2022-10-05 12:56:10 +02:00
M0stafaRady 8b242ecc8e Apply automatic changes to Manifest and README.rst 2022-10-05 10:29:42 +00:00
M0stafaRady 650483eaa2 fix some typos on mgmt_protect 2022-10-05 03:27:46 -07:00
M0stafaRady 7de6bdf75e Apply automatic changes to Manifest and README.rst 2022-10-04 17:58:52 +00:00
M0stafaRady 4b762da8e6 merge with caravel_redesign 2022-10-04 10:57:56 -07:00
M0stafaRady 2f71281af0 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-04 10:56:04 -07:00
M0stafaRady e2b345dcbb Add new test user_pass_thru_rd 2022-10-04 10:55:53 -07:00
M0stafaRady 0bd6c73b7b update verify_cocotb script to merge coverage 2022-10-04 10:47:07 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
Mohamed Shalan 599ee23610
Merge pull request #137 from efabless/fix_caravan_gpio_default 
Changed gpio_defaults_block_14 to gpio_defaults_block_25
 2022-10-04 19:03:46 +02:00
Mohamed Shalan df08268f8a
Merge pull request #142 from efabless/remove_mgmt_protect_tristates 
Remove mgmt protect tristates
 2022-10-04 12:55:34 +02:00
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
RTimothyEdwards d3ff5ab8fa Apply automatic changes to Manifest and README.rst 2022-10-03 20:16:32 +00:00
Tim Edwards de9605a01b Modified the mgmt_protect module to change the tristate outputs to 
zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs.  The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL.  This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
 2022-10-03 16:11:02 -04:00
M0stafaRady ef9c2e408b fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
M0stafaRady 5788214f6d Apply automatic changes to Manifest and README.rst 2022-10-03 16:02:59 +00:00
M0stafaRady 37244a2514 add 3 regressions r_rtl , r_gl,r_sdf 2022-10-03 09:01:08 -07:00
M0stafaRady c4859c8789 fix bug at reading from debug registers 2022-10-03 08:57:23 -07:00
M0stafaRady e81416bb51 add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
M0stafaRady e945c3b882 fix bug at mgmt_gpio_out by increasing the number of phases 2022-10-03 05:45:55 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00
M0stafaRady a00d62ebcf Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-03 04:03:22 -07:00
M0stafaRady 55f6f56921 update verify_cocotb script to run iverilog inside a docker 2022-10-03 01:56:08 -07:00
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
M0stafaRady 03527360e3 Apply automatic changes to Manifest and README.rst 2022-10-02 13:57:05 +00:00
M0stafaRady e661740208 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:55:52 -07:00
M0stafaRady f3792b8421 merge with caravel_redesign 2022-10-02 06:55:41 -07:00
M0stafaRady 9812aedaa1
Update README.md 2022-10-02 15:50:18 +02:00
M0stafaRady f0494ef4b1 update make file to take user_project_wrapper file as input for iverilog 2022-10-02 06:48:29 -07:00
M0stafaRady 927c216a6b Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:38:32 -07:00
M0stafaRady 752d12928b fix iverlog command for the new structure 2022-10-02 06:38:22 -07:00
M0stafaRady d8a4b812e8 update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode 2022-10-02 06:37:12 -07:00