c8da85cc24
[Doc] Update naming convention for OpenFPGA architecture files
2022-03-20 10:51:55 +08:00
a1e2d9c864
[Arch] Add a new example openfpga arch where clock ports are independent
2022-03-20 10:50:31 +08:00
9f7a182433
[Arch] Typo
2022-02-24 09:51:26 -08:00
fdaf97e60d
[Test] Update test case by using GPIO with config_done signals
2022-02-24 09:49:34 -08:00
e443a4567d
[Arch] Typo
2022-02-23 22:09:26 -08:00
b27a04eb24
[Test] Now test case has a config done CCFF
2022-02-23 22:07:11 -08:00
62b4a0b7ff
[Flow] Add openfpga arch for DSP with registers
2022-01-02 19:59:33 -08:00
7598455497
[Doc] Update naming convention for architecture files
2022-01-02 19:51:09 -08:00
b8d5920529
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-28 15:45:58 -07:00
2eef21a1af
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
82e77b42c5
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
2021-10-09 20:43:55 -07:00
d2859ca1c8
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
2021-10-05 10:56:20 -07:00
fbef22b494
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
2021-10-04 16:39:53 -07:00
86e7c963f8
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
2021-10-02 22:19:20 -07:00
7ba5d27ea7
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
2021-10-01 17:02:35 -07:00
fa57117f50
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
2021-10-01 10:19:51 -07:00
41cc375746
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
2021-09-29 16:34:40 -07:00
4968f0d11f
Merge branch 'master' into qlbank_sr
2021-09-28 14:20:30 -07:00
80232fc459
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
2021-09-28 12:36:36 -07:00
4c04c0fbd7
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
2021-09-28 12:35:42 -07:00
4aed045cdd
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
2021-09-28 11:34:20 -07:00
a98df811ed
[Arch] Bug fix: wrong circuit model name was used for CCFF
2021-09-22 15:50:47 -07:00
53da5d49fe
[Arch] Correct XML syntax errors
2021-09-22 15:48:14 -07:00
3cfd5c3531
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
2021-09-22 15:04:59 -07:00
212c5bd642
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
2021-09-22 15:04:19 -07:00
d0fe12fadd
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
2021-09-22 10:03:39 -07:00
0450d57d82
[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
2021-09-20 16:05:01 -07:00
cd2978a434
[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
2021-09-20 11:13:02 -07:00
6be3c64f1c
[Arch] Add an example architecture using the physical design friendly memory bank organization
2021-09-09 09:22:27 -07:00
dcb89cb16b
[Arch] Patch architecture due to missing mode bit definition
2021-07-02 11:41:29 -06:00
fd85f956c9
[Arch] Update k4n4 arch with true multi-mode flip-flop
2021-07-02 11:08:39 -06:00
f77b81fe5b
[Arch] recover the mem16k arch as it is used in other test cases
2021-04-28 15:05:30 -06:00
117cea295d
[Arch] Patch architecture to be compatible with pin names of DPRAM cell
2021-04-28 11:28:23 -06:00
ec4b60f3cc
[Arch] Add example arch using 1-kbit DPRAM
2021-04-28 10:47:17 -06:00
be98775ae5
[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
2021-04-28 10:45:10 -06:00
834657f2da
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
2021-04-27 23:41:14 -06:00
0f8aaae2bc
[Arch] Patch architecture using 16kbit dual port RAM
2021-04-27 19:54:34 -06:00
a3a98fa21d
[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
2021-04-24 14:56:10 -06:00
4f454abfde
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
2021-04-24 14:01:42 -06:00
ddcdb35b28
[Arch] Bug fix in single-mode 8-bit DSP architectures
2021-04-24 13:30:03 -06:00
ce6018e123
[Arch] Enriched DFF model to support active-low/high FFs
2021-04-21 22:48:31 -06:00
9d9840d9b7
[Arch] Add architecture using multi-mode DFFs
2021-04-21 19:49:48 -06:00
16e02ef485
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
2021-04-16 20:47:39 -06:00
4239bb4e68
[Arch] Patch architecture files using multi-mode DFFs
2021-04-16 19:59:55 -06:00
f2f7f010ea
[Arch] Add new architectures using DFF with reset in VPR
2021-04-16 19:26:18 -06:00
64294ae4eb
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
fdec72b5bc
[Arch] Add an example architecture with 8-bit single-mode multiplier
2021-03-23 15:35:06 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
baf162e401
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
2021-03-10 22:45:19 -07:00
2daa770319
[Arch] Update openfpga architecture to include quicklogic cell sim
2021-03-08 21:40:29 -07:00
4c2a88e27f
[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
2021-02-24 11:51:10 -07:00
0ce9b66c75
[Arch] Add a dummy adder lut circuit model to support HDL simulation
2021-02-24 10:09:44 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
b81b74aa7c
[Arch] Patch architecture to support superLUT-related XML syntax
2021-02-09 20:23:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
2f1aceda67
[Doc] Update documentation about architecture naming rules
2021-01-12 18:01:24 -07:00
9fa49c401c
[Arch] Add openfpga architecture which uses 4 global clocks
2021-01-12 18:00:22 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
dfb3e32147
[Arch] Add openfpga archiecture for registerable I/O
2021-01-10 10:54:41 -07:00
0b74575606
[Arch] Update arch using global reset tile port
2021-01-09 18:04:55 -07:00
7b24da267a
[Arch] Remove port size XML syntax
2021-01-09 16:30:46 -07:00
9f12b25a24
[Arch] Add port size to global port defined thru tile annotation
2021-01-09 16:23:28 -07:00
0f5f0a3527
[Arch] Add x,y coordinates to global port definition
2021-01-09 15:50:09 -07:00
a14a56772a
[Arch] Introduce new XML syntax for global port in tile annotation
2021-01-09 15:48:42 -07:00
a813c9016b
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
2021-01-04 17:39:13 -07:00
c97a92d628
[Arch] Patch openfpga architecture for ccff circuit model port requirement
2021-01-04 17:15:50 -07:00
294ad97d38
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
2021-01-04 14:56:49 -07:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
...
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
412fb5bb31
[Arch] Bug fix due to valid default value parser
2020-12-02 17:51:50 -07:00
c7604ab94f
[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
2020-11-30 18:02:00 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
17070c6405
[Doc] Update README in openfpga arch directory for native fracturable LUT design
2020-11-25 22:19:20 -07:00
f6a667de58
[Arch] Add openfpga architecture using native fracturable LUT
2020-11-25 22:18:03 -07:00
fefba0db59
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
1d993296d8
[Flow] Example of using test variable in task conf
2020-11-25 17:25:12 -07:00
f29916921a
[Arch] Add openfpga arch for using global clocks from tiles
2020-11-10 19:20:08 -07:00
75ce4b5e25
[Arch] Fine tune example arch
2020-11-10 14:38:47 -07:00
d127304760
[Arch] Update sample arch using local clock from physical tile ports
2020-11-10 14:31:58 -07:00
4ca2a129c2
[Arch] Add an sample architecture where global clock port is defined from tile ports
2020-11-10 11:47:03 -07:00
70734abc35
[Arch] Remove QN from stdcell arch
2020-11-06 11:20:13 -07:00
2aab8bf910
[Arch] Use single-output DFF for a standard cell FPGA
2020-11-06 10:26:39 -07:00
tangxifan
Aram Kostanyan
Nachiket Kapre
AurelienAlacchi
ganeshgore