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1193 Commits

Author SHA1 Message Date
Aram Kostanyan 397f2e71f1 Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task. 2022-01-19 20:43:26 +05:00
Aram Kostanyan bd158311c5 Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark. 2022-01-18 14:07:41 +05:00
Aram Kostanyan 588ee14920 Merge branch 'master' into issue-483 2022-01-18 13:38:12 +05:00
Aram Kostanyan fb2e4377c8 Added missing changes from previous commit. 2022-01-17 19:42:40 +05:00
Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
Awais Abbas 469b3a960c basic reg test updated 2022-01-14 15:44:26 +05:00
Awais Abbas 793e40cb95 basic_reg test for yosys-only flow added in OpenFPGA regression test scripts 2022-01-14 15:39:26 +05:00
Awais Abbas 598c5e6b75 Test case for yosys-only flow added 2022-01-14 15:37:47 +05:00
Awais Abbas fc52a4696c Yosys only support added in OpenFPGA 2022-01-06 14:44:11 +05:00
tangxifan 27caeb1d1f [Arch] Patched VPR arch 2022-01-02 20:47:22 -08:00
tangxifan 384a1e58d6 [Arch] Patch architecture using DSP with registers 2022-01-02 20:44:43 -08:00
tangxifan e3baec63f8 [Arch] Bug fix on architecture with registerable DSP 2022-01-02 20:35:48 -08:00
tangxifan f667065f75 [Arch] Bug fix in DSP with registers architecture 2022-01-02 20:34:26 -08:00
tangxifan 9c476ed5db [Arch] Syntax error fix 2022-01-02 20:27:00 -08:00
tangxifan 628191da5f [Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests 2022-01-02 20:21:58 -08:00
tangxifan 824a03bdca [Flow] Patch new test case 2022-01-02 20:20:36 -08:00
tangxifan 48355d1fc3 [Benchmark] Add pipelined multiplier benchmark to test DSP block with registers 2022-01-02 20:16:59 -08:00
tangxifan 55da99f4ca [Flow] Add a new test case to validate DSP with registers 2022-01-02 20:08:23 -08:00
tangxifan 62b4a0b7ff [Flow] Add openfpga arch for DSP with registers 2022-01-02 19:59:33 -08:00
tangxifan 7598455497 [Doc] Update naming convention for architecture files 2022-01-02 19:51:09 -08:00
tangxifan 48491fcf52 [Flow] Add example architecture for DSP with input and output registers 2022-01-02 19:47:39 -08:00
tangxifan 81966c2131 [Doc] Update README for DSP blocks 2022-01-02 18:27:37 -08:00
nadeemyaseen-rs 236910cde4 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-09 00:00:21 +05:00
nadeemyaseen-rs 06fb4b0ece Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-25 00:00:22 +05:00
coolbreeze413 3c14373abf revert unnecessary task.conf changes 2021-11-19 19:07:09 +05:30
coolbreeze413 9ca8ab4fa2 minor change to task.conf to check CI 2021-11-19 18:49:37 +05:30
coolbreeze413 b86bd1ca68 re-enable counter_5clock,sdc_controller, lut_adder tests 2021-11-19 18:06:06 +05:30
coolbreeze413 31379062e3 remove minor comments 2021-11-18 18:40:15 +05:30
nadeemyaseen-rs 1ea56b2d18 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-18 00:00:55 +05:00
coolbreeze413 91094305bd enable all tests except 15 and 19 2021-11-17 20:56:12 +05:30
Lalit Sharma fe74c42252 Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 01:46:06 -08:00
coolbreeze413 840fa399c6 enable single counter test (fails, needs debug) 2021-11-09 21:36:33 +05:30
coolbreeze413 3fa373f8bc add plugins, set yosys install for plugin 2021-11-04 07:22:09 +05:30
Aram Kostanyan a707226ba6 Added 'basic_tests/verific_test' test case into regression tests suite. 2021-11-01 18:33:33 +05:00
Aram Kostanyan b332a5a1b4 Added 'basic_tests/verific_test' test-case. 2021-11-01 18:20:57 +05:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 0d882f57b1
Merge branch 'master' into yosys+verific_support 2021-10-30 22:49:21 -07:00
tangxifan 0d14aa4cb8 [Flow] Add comments to clarify the limitations 2021-10-30 19:17:11 -07:00
tangxifan 7f999d03c6 [Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade 2021-10-30 18:05:39 -07:00
tangxifan 370e3fef83 [Test] Now use pre-configured testbench when verifying signal gen microbenchmarks 2021-10-30 18:03:59 -07:00
tangxifan 7455990ead [Flow] bug fix 2021-10-30 16:52:32 -07:00
tangxifan c8e9dfbeda [Test] bug fix 2021-10-30 16:50:57 -07:00
tangxifan 27b82d1473 [Flow] bug fix 2021-10-30 16:09:31 -07:00
tangxifan a4cfc84930 [Test] Bug fix 2021-10-30 16:00:47 -07:00
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan 6277234125 [Flow] bug fix in BRAM-oriented yosys scripts 2021-10-30 15:34:30 -07:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan e6cc3c4942 [Flow] Enable flatten for dff-related yosys scripts 2021-10-30 15:12:34 -07:00
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 8dea7e80e6 [Flow] Update yosys script to not use sdff and dffe 2021-10-30 14:56:54 -07:00