Commit Graph

76 Commits

Author SHA1 Message Date
tangxifan dafab3907e refactored routing module generation and verilog writing 2019-10-23 11:46:55 -06:00
tangxifan 071757dc52 add module nets to connect grids and sbs 2019-10-15 16:08:51 -06:00
tangxifan 173b886314 add module name generation for pb_types 2019-10-07 21:09:54 -06:00
tangxifan 1e183e7885 refactored shared config bits calculation 2019-10-06 16:57:53 -06:00
tangxifan 393f0b0ac3 align formal verification port inside refactored routing blocks 2019-10-05 21:16:48 -06:00
tangxifan c920047ee8 refactored Verilog generation for connection blocks 2019-10-05 18:14:23 -06:00
tangxifan 2d7e8d9811 add check codes for memory buses 2019-10-05 11:07:26 -06:00
tangxifan 6b301d9f44 Merge branch 'dev' into refactoring 2019-10-04 22:47:29 -06:00
tangxifan b905c0c68c refactored memory module Verilog generation for scan-chains 2019-10-04 22:45:45 -06:00
Baudouin Chauviere 01ff484158 Explicit verilog passing all tests 2019-10-02 10:22:28 -06:00
Baudouin Chauviere 6b3e1fd410 Get backup verilog_routing.c 2019-10-02 08:54:56 -06:00
tangxifan b082e60c10 start refactoring instanciation of memory modules 2019-09-29 18:20:56 -06:00
tangxifan 1983e56557 make local configuration bus generation more general 2019-09-28 21:02:14 -06:00
tangxifan 1e187f3d15 start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
tangxifan 167778cf57 refactoring MUX Verilog instanciation in Switch block 2019-09-27 16:05:47 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 091bbd4d9c start refactoring the num_config_bits for circuit model 2019-09-26 22:53:07 -06:00
tangxifan f0589cc2cf refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
tangxifan 05eaa412b1 refactored short-connection of switch block 2019-09-26 14:31:05 -06:00
tangxifan 5bb40e7f74 refactored local wire generation for Switch block 2019-09-25 21:05:02 -06:00
tangxifan 2b0e2615fa refactored sram port addition to module manager 2019-09-25 16:09:58 -06:00
tangxifan c911f15a67 add formal verification port to SB Verilog generation 2019-09-23 21:15:45 -06:00
tangxifan d2ddbc19a3 refactoring the reserved sram port generation 2019-09-22 16:38:16 -06:00
tangxifan 2c4372c506 add reserved BLB/WL port naming 2019-09-22 12:16:43 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
tangxifan 2294aecef2 remove old codes and compact new codes 2019-09-16 20:19:14 -06:00
tangxifan c5ee81541a remove dead codes in routing module generation 2019-09-16 18:47:01 -06:00
tangxifan 0963852091 remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
2019-09-16 18:38:37 -06:00
tangxifan d83cad7c2e refactoring Verilog generation for routing channels 2019-09-16 17:35:51 -06:00
tangxifan 1118b28397 use single subckt for switch box again, to abolish the multi-module subckt 2019-08-13 16:11:04 -06:00
tangxifan 32e3a556b9 bug fixing herited from explicit mapping 2019-07-17 09:26:05 -06:00
tangxifan e9154b1f74 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 14:42:45 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
tangxifan 78578f66c5 bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG 2019-07-13 14:48:32 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
Baudouin Chauviere ae05c553d5 Top module done 2019-07-08 09:48:33 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00
tangxifan 57616361c2 fixed critical bugs in cb configuration port indices 2019-06-26 14:58:52 -06:00
tangxifan d50fb7ee19 fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00