tangxifan
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ef4d15df4e
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reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
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tangxifan
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392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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tangxifan
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c004699a14
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complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
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tangxifan
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74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
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tangxifan
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f57495feba
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Now we can also auto-generate the Verilog for a mux2 std cell
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2019-08-06 15:19:01 -06:00 |
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tangxifan
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afa468a442
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hotfix in minor Verilog generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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b4f3dfc82d
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bug fixing for local encoder's bitstream generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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3a490fdd59
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bug fixing on the port map alignment
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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890ff05628
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bug fixing and get ready for testing
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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c08c136844
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set a working range for the encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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386bddacd1
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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557b1af633
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add Verilog generation for local encoders, bitstream upgrade TODO
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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003883b13b
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implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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32e3a556b9
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bug fixing herited from explicit mapping
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2019-07-17 09:26:05 -06:00 |
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tangxifan
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8b8e18a8de
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bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
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tangxifan
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a2505ff16a
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turn on std cell explicit port map
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2019-07-17 08:36:09 -06:00 |
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tangxifan
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dcc96bf7f5
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bug fixing
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2019-07-17 08:25:52 -06:00 |
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tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
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tangxifan
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e9154b1f74
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 14:42:45 -06:00 |
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tangxifan
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115411941b
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:15:45 -06:00 |
Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
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e602006a07
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-16 12:45:13 -06:00 |
AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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tangxifan
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bcc6346533
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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tangxifan
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4c6e245885
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speed-up the unique routing process
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2019-07-14 12:22:00 -06:00 |
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tangxifan
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b690e702f6
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adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
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tangxifan
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aa4cd850ae
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try to optimize the runtime of routing uniqueness detection
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2019-07-13 18:10:34 -06:00 |
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tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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tangxifan
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cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
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2019-07-11 21:02:09 -06:00 |
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Baudouin Chauviere
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c9b84f61c9
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Hot fix
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2019-07-11 17:39:02 -06:00 |
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Baudouin Chauviere
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d0cd5a2bc1
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Hot fix
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2019-07-11 17:27:31 -06:00 |
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tangxifan
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9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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Baudouin Chauviere
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f4be375637
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Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
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tangxifan
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a90316e9f4
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
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tangxifan
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acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
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Baudouin Chauviere
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6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
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Baudouin Chauviere
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0a978db866
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Fix regression test
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2019-07-10 14:16:34 -06:00 |
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tangxifan
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b7f9831bd2
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add statistics for unique GSBs
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2019-07-10 13:08:03 -06:00 |
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tangxifan
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c6a4d29ed8
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Merge branch 'tileable_routing' into dev
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2019-07-10 12:05:43 -06:00 |
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tangxifan
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57ae5dbbec
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bug fixing for rectangle FPGA sizes
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2019-07-09 20:47:52 -06:00 |
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tangxifan
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edfe3144c3
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update profiling, found where runtime is lost
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2019-07-09 20:28:01 -06:00 |