80e982fb39
minor file format fix in fabric bitstream XML
2020-07-26 21:35:48 -06:00
b3ad04fd1e
minor file format fix in fabric bitstream XML
2020-07-26 21:33:47 -06:00
861e346830
minor bug fix in fabric bitstream XML writer
2020-07-26 21:31:08 -06:00
92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
62fd0947f5
using a unified string to replace multi net names to save memory of bitstream database
2020-07-08 16:28:20 -06:00
033c92c365
precisely reserve memory for child blocks in bitstream manager
2020-07-03 22:47:21 -06:00
46f038c829
bug fix in grid config block allocation
2020-07-03 20:46:04 -06:00
f040fc78a9
now reserve blocks in bitstream manager can accurately capture the size
2020-07-03 20:06:12 -06:00
8067a13346
bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
2020-07-03 15:56:20 -06:00
2a9377b3f4
use encoded address in storage of fabric bitstream to save memory
2020-07-03 15:12:29 -06:00
70d9678578
reserve child block in bistream manager
2020-07-03 14:04:10 -06:00
2783fda344
use index range instead of vector for block bitstream
2020-07-03 11:42:38 -06:00
6ea857ae6c
use fast method to inquire number of bits and blocks in bitstream databases
2020-07-03 10:55:25 -06:00
7ca1a5bdc1
Fabric bitstream now allocates vectors in conditions for memory efficiency
2020-07-03 10:17:03 -06:00
8a45e48a1c
minor fix
2020-07-02 22:27:48 -06:00
246b4d5ac6
reserve block bits to save memory
2020-07-02 21:52:32 -06:00
dee4be96af
reserve all the input/output net storage in bitstream manager
2020-07-02 19:17:34 -06:00
81c9fcb7c0
bug fix when optimizing the fabric bitstream data structure
2020-07-02 16:41:32 -06:00
9608cefa86
remove id vector in fabric bitstream database and replace with more memory efficient implementation
2020-07-02 16:08:50 -06:00
9f19c36a89
use char in fabric bitstream to save memory footprint
2020-07-02 15:56:50 -06:00
405824081b
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
2020-07-02 15:28:52 -06:00
b85af57971
optimizing fabric bitsteream memory footprint
2020-07-02 12:39:18 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
51e1559352
add fabric bitstream support for memory bank configuration protocol
2020-06-11 19:31:13 -06:00
8298bbff78
bug fixed in the fabric bitstream for frame-based configurable memories.
2020-06-11 19:31:10 -06:00
65df309419
bug fixing for frame-based configuration protocol and rename some naming function to be generic
2020-06-11 19:31:10 -06:00
cff5b5cfc1
break the configuration testbench. This commit is to spot which modification leads to the problem
2020-06-11 19:31:10 -06:00
85921dcc05
add fabric bitstream builder for frame-based configuration protocol
2020-06-11 19:31:10 -06:00
4a0e1cd908
add fabric bitstream data structure and deploy it to Verilog testbench generation
2020-06-11 19:31:10 -06:00
8c14cced84
start improve fabric bitstream database to support frame-based configuration protocol
2020-06-11 19:31:09 -06:00
d325bede68
add fabric bitstream writer
2020-04-21 12:02:10 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
b80e26e711
update bitstream generator to use sorted edges
2020-03-08 15:36:47 -06:00
3807a940f4
fixed critical bugs in bitstream generation and now we pass microbenchmarks
2020-02-28 16:45:50 -07:00
410dcf6ab6
debugged LUT bitstream
2020-02-26 11:42:18 -07:00
a26d31b87f
make write bitstream online
2020-02-26 11:09:23 -07:00
759758421d
found the bug in physical pb mode bits and fixed
2020-02-25 23:45:49 -07:00
075264e3e3
debugging LUT bitstream generation
2020-02-25 23:29:16 -07:00
2c44c70557
bring pb interconnection bitstream generation online
2020-02-25 00:28:06 -07:00
04c69d30c2
start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
2020-02-24 19:38:02 -07:00
712eeb1340
bring bitstream generator for routing modules online
2020-02-23 22:09:46 -07:00
86c7c24701
add fabric bitstream generation online
2020-02-23 20:58:17 -07:00
8723007f68
Bring mux bitstream generation online
2020-02-23 20:53:24 -07:00
51439ba3b4
add bitstream writer to be integrated
2020-02-23 20:40:18 -07:00
2d17395e13
start integrating fpga_bitstream. Bring data structures online
2020-02-22 23:04:42 -07:00
tangxifan