252 Commits

Author	SHA1	Message	Date
tangxifan	f00acf1e62	[code] fixed all the compiler warnings under openfpga/src	2023-01-31 12:51:52 -08:00
tangxifan	e2debd2dde	[engine] add missing header files after coding formatter sorts the include files	2022-10-06 18:08:57 -07:00
tangxifan	6d31b319a2	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
tangxifan	dfe30df462	[engine] resolve compilation warnings	2022-08-17 16:32:21 -07:00
tangxifan	e0ae851e28	[engine] correcting compilation errors due to vpr upgrade	2022-08-17 16:25:12 -07:00
tangxifan	8ab090651a	[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports	2022-03-16 20:51:37 +08:00
tangxifan	235887e03a	[FPGA-Verilog] Fixed a bug on config-enable signals	2022-02-23 22:35:23 -08:00
tangxifan	086642d134	[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly	2022-02-23 15:33:24 -08:00
tangxifan	1c18d14ad5	[FPGA-Verilog] Add big/little endian support to output ports	2022-02-19 09:23:48 -08:00
tangxifan	3e43a60fdc	[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks	2022-02-19 09:15:38 -08:00
tangxifan	671188dfa4	[FPGA-Verilog] Now support big/little-endian in bus group	2022-02-18 23:05:03 -08:00
tangxifan	790715f46a	[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator	2022-02-18 15:41:35 -08:00
tangxifan	401f673f16	[FPGA-Verilog] Streamline codes by using APIs	2022-02-18 14:47:36 -08:00
tangxifan	c16ea8d082	[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches	2022-02-18 14:34:32 -08:00
tangxifan	a4dc86a33d	[FPGA-Verilog] Now output atom block name removal has a dedicated function	2022-02-18 14:30:46 -08:00
tangxifan	f5dd89bbd9	[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used	2022-02-18 14:08:03 -08:00
tangxifan	0d620888ab	[FPGA-Verilog] Now instance can output bus ports with all the pins	2022-02-18 12:03:26 -08:00
tangxifan	aa375fd7a4	[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator	2022-02-18 11:31:11 -08:00
tangxifan	6da0ede9b0	[FPGA-Verilog] Adding bus group support to all Verilog testbench generators	2022-02-17 23:48:44 -08:00
tangxifan	c96f0d199d	[FPGA-Verilog] Adding bus group support in Verilog testbenches	2022-02-17 23:14:28 -08:00
tangxifan	e67f8ad8b2	[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase	2022-02-15 17:19:50 -08:00
tangxifan	be8f18310d	[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances	2022-02-14 17:16:26 -08:00
tangxifan	d3f68db228	[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches	2022-02-14 17:00:54 -08:00
tangxifan	34e192c5ca	[FPGA-Verilog] Fixed a bug on wiring FPGA global ports	2022-02-14 15:21:29 -08:00
tangxifan	8d48492ec0	[FPGA-Verilog] Add clock ports to the white list when adding postfix	2022-02-14 11:09:00 -08:00
tangxifan	5794561f7b	[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench	2022-02-14 10:39:27 -08:00
tangxifan	2ca73d79e4	[FPGA-Verilog] Fixed the bug on pin constraints	2022-02-13 22:08:06 -08:00
tangxifan	b1377f0d34	[FPGA-Verilog] Fix syntax errors	2022-02-13 20:29:05 -08:00
tangxifan	6e132aace4	[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module	2022-02-13 20:26:21 -08:00
tangxifan	fb4106de19	[FPGA-Verilog] Fixed a bug in naming mismatch	2022-02-13 20:06:35 -08:00
tangxifan	a068237082	[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks	2022-02-13 19:55:16 -08:00
tangxifan	1c94d0f285	[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``	2022-02-01 13:25:09 -08:00
tangxifan	f311a034bb	[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``	2022-02-01 12:17:02 -08:00
tangxifan	2b8e2de0c9	[FPGA-Verilog] Fix bugs	2022-01-31 14:23:04 -08:00
tangxifan	6c29c286bc	[FPGA-Verilog] Fix a bug which cause errors	2022-01-31 14:06:58 -08:00
tangxifan	63f44adf15	[FPGA-Verilog] Now have a new option ``--use_relative_path``	2022-01-31 12:48:05 -08:00
Emin Cetin	6c2c4e8b14	adding comment	2022-01-28 08:57:45 +03:00
Emin Cetin	f9b47c3b34	missing semicolon	2022-01-27 16:49:04 +03:00
Emin Cetin	8f7ee4e338	changing condition of bitstream downloading	2022-01-27 11:49:55 +03:00
tangxifan	62b57b05d2	[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``	2022-01-25 12:09:08 -08:00
tangxifan	ff264c00a2	Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream	2021-10-31 11:51:34 -07:00
tangxifan	91627abe12	[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided	2021-10-30 11:53:46 -07:00
tangxifan	546350ae41	[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks	2021-10-10 23:19:39 -07:00
tangxifan	202b50c0e3	[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why	2021-10-10 20:57:23 -07:00
tangxifan	de3275e9ba	[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains	2021-10-10 16:56:07 -07:00
tangxifan	6aa4991314	[FPGA-Verilog] Bug fix	2021-10-09 21:34:07 -07:00
tangxifan	34575f7222	[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank	2021-10-09 20:39:45 -07:00
tangxifan	19a551e641	[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region	2021-10-09 16:44:04 -07:00
tangxifan	8f5f30792f	[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface	2021-10-08 15:25:37 -07:00
tangxifan	54a8809b3c	[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains	2021-10-06 16:49:28 -07:00