tangxifan
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1c9da96f59
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[lib] move io_location_map to libpcf
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2022-07-26 16:00:28 -07:00 |
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tangxifan
|
27fea8bbbe
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[lib] Merge librepackdc into libpcf
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2022-07-26 15:54:32 -07:00 |
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tangxifan
|
23f98d6a3b
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[engine] fixed a few bugs
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2022-07-26 13:55:29 -07:00 |
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tangxifan
|
85bcb36f34
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[engine] fix compiler errors
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2022-07-26 12:25:40 -07:00 |
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tangxifan
|
0862eceed0
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[engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!!
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2022-07-26 12:17:45 -07:00 |
taoli4rs
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3762a3aae4
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Code clean up based on review.
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2022-07-20 14:34:44 -07:00 |
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taoli4rs
|
cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
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tangxifan
|
a7e87b9432
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[FPGA-Bitstream] note limitations
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2022-05-25 18:38:01 +08:00 |
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tangxifan
|
ffac5a66e1
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[FPGA-Bitstream] Now encode address bits to save memory in bitstream database
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2022-05-25 17:45:08 +08:00 |
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tangxifan
|
bf1a81fbb5
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[FPGA-bitstream] add timer to computing intensive functions
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2022-05-25 14:52:32 +08:00 |
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tangxifan
|
a20f6eaf06
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[Engine] Fixed a few bugs
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2022-04-10 21:29:38 +08:00 |
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tangxifan
|
755be78b39
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[Engine] Now GSB output file contains segments name and pin name in SB module
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2022-04-10 21:22:30 +08:00 |
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tangxifan
|
6171abdf95
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[FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats
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2022-03-29 19:41:15 +08:00 |
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tangxifan
|
4d67864c2c
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[Engine] Now global port can be connected partial pins of a tile port
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2022-03-20 11:36:03 +08:00 |
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tangxifan
|
8ab090651a
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[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports
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2022-03-16 20:51:37 +08:00 |
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tangxifan
|
235887e03a
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[FPGA-Verilog] Fixed a bug on config-enable signals
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2022-02-23 22:35:23 -08:00 |
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tangxifan
|
086642d134
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[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly
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2022-02-23 15:33:24 -08:00 |
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tangxifan
|
1c18d14ad5
|
[FPGA-Verilog] Add big/little endian support to output ports
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2022-02-19 09:23:48 -08:00 |
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tangxifan
|
3e43a60fdc
|
[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks
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2022-02-19 09:15:38 -08:00 |
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tangxifan
|
671188dfa4
|
[FPGA-Verilog] Now support big/little-endian in bus group
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2022-02-18 23:05:03 -08:00 |
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tangxifan
|
790715f46a
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[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
|
2022-02-18 15:41:35 -08:00 |
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tangxifan
|
401f673f16
|
[FPGA-Verilog] Streamline codes by using APIs
|
2022-02-18 14:47:36 -08:00 |
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tangxifan
|
c16ea8d082
|
[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches
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2022-02-18 14:34:32 -08:00 |
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tangxifan
|
a4dc86a33d
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[FPGA-Verilog] Now output atom block name removal has a dedicated function
|
2022-02-18 14:30:46 -08:00 |
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tangxifan
|
f5dd89bbd9
|
[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
|
2022-02-18 14:08:03 -08:00 |
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tangxifan
|
0d620888ab
|
[FPGA-Verilog] Now instance can output bus ports with all the pins
|
2022-02-18 12:03:26 -08:00 |
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tangxifan
|
aa375fd7a4
|
[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator
|
2022-02-18 11:31:11 -08:00 |
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tangxifan
|
6da0ede9b0
|
[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
|
2022-02-17 23:48:44 -08:00 |
|
tangxifan
|
c96f0d199d
|
[FPGA-Verilog] Adding bus group support in Verilog testbenches
|
2022-02-17 23:14:28 -08:00 |
|
tangxifan
|
38601f325b
|
[Engine] Add bus group to OpenFPGA core
|
2022-02-17 17:28:55 -08:00 |
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tangxifan
|
e67f8ad8b2
|
[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase
|
2022-02-15 17:19:50 -08:00 |
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tangxifan
|
be8f18310d
|
[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances
|
2022-02-14 17:16:26 -08:00 |
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tangxifan
|
d3f68db228
|
[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches
|
2022-02-14 17:00:54 -08:00 |
|
tangxifan
|
34e192c5ca
|
[FPGA-Verilog] Fixed a bug on wiring FPGA global ports
|
2022-02-14 15:21:29 -08:00 |
|
tangxifan
|
8d48492ec0
|
[FPGA-Verilog] Add clock ports to the white list when adding postfix
|
2022-02-14 11:09:00 -08:00 |
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tangxifan
|
5794561f7b
|
[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench
|
2022-02-14 10:39:27 -08:00 |
|
tangxifan
|
2ca73d79e4
|
[FPGA-Verilog] Fixed the bug on pin constraints
|
2022-02-13 22:08:06 -08:00 |
|
tangxifan
|
b1377f0d34
|
[FPGA-Verilog] Fix syntax errors
|
2022-02-13 20:29:05 -08:00 |
|
tangxifan
|
6e132aace4
|
[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module
|
2022-02-13 20:26:21 -08:00 |
|
tangxifan
|
fb4106de19
|
[FPGA-Verilog] Fixed a bug in naming mismatch
|
2022-02-13 20:06:35 -08:00 |
|
tangxifan
|
a068237082
|
[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks
|
2022-02-13 19:55:16 -08:00 |
|
tangxifan
|
1c94d0f285
|
[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``
|
2022-02-01 13:25:09 -08:00 |
|
tangxifan
|
f311a034bb
|
[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``
|
2022-02-01 12:17:02 -08:00 |
|
tangxifan
|
2b8e2de0c9
|
[FPGA-Verilog] Fix bugs
|
2022-01-31 14:23:04 -08:00 |
|
tangxifan
|
6c29c286bc
|
[FPGA-Verilog] Fix a bug which cause errors
|
2022-01-31 14:06:58 -08:00 |
|
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
|
2022-01-31 12:48:05 -08:00 |
Emin Cetin
|
6c2c4e8b14
|
adding comment
|
2022-01-28 08:57:45 +03:00 |
|
Emin Cetin
|
f9b47c3b34
|
missing semicolon
|
2022-01-27 16:49:04 +03:00 |
|
Emin Cetin
|
8f7ee4e338
|
changing condition of bitstream downloading
|
2022-01-27 11:49:55 +03:00 |
|
tangxifan
|
a9a56686e2
|
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
|
2022-01-26 11:10:29 -08:00 |