Commit Graph

119 Commits

Author SHA1 Message Date
tangxifan fbb5c0cf8f [Doc] Add pin constraints to documentation 2021-01-19 18:04:45 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 0c808bec41 [Doc] Add clarification for defining multi-bit global tile ports 2021-01-09 20:00:16 -07:00
tangxifan 2324edc522 [Doc] Update documentation for upgraded tile annotation 2021-01-09 18:55:16 -07:00
tangxifan 226f6b8d6d [Doc] Update documentation about FF circuit models to show capability in modeling SCFFs 2021-01-04 18:30:04 -07:00
tangxifan 406edeec89 [Doc] Typo fix 2020-12-04 15:07:02 -07:00
tangxifan 4fe190fa7e [Doc] Bug fix in LUT circuit model documentation 2020-12-04 14:44:27 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan cc0114459a [Doc] Enrich examples for LUT circuit models 2020-11-26 13:03:12 -07:00
tangxifan 62e804215b [Doc] Add svg figures for LUT examples 2020-11-26 12:35:39 -07:00
tangxifan b857135f4e [Doc] Add clarification about which cells are applicable for signal initialization 2020-11-23 15:19:15 -07:00
tangxifan 2b9a97729e [Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models 2020-11-23 15:09:47 -07:00
tangxifan fd0e6814ea [Doc] Update documentation about the pre-processing flags 2020-11-22 20:33:15 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 056b7c0c79 [Doc] Update documentation about CCFF circuit model examples 2020-11-06 12:22:22 -07:00
tangxifan 849ecc7fc0 [Doc] Add notes for using the is_data_io syntax 2020-11-05 09:30:19 -07:00
tangxifan 9bce2f3818 [Doc] Update documentation for new XML syntax "is_data_io" 2020-11-05 09:28:46 -07:00
tangxifan be7f7592ae [Doc] Update documentation about don't care bit in frame address 2020-10-30 22:13:28 -06:00
tangxifan 7e940980e1 [Doc] Update documentation about configuration regions for frame-based protocol 2020-10-30 21:52:01 -06:00
tangxifan c2c384e24b [Doc] update documentation about memory bank definition 2020-10-29 17:04:25 -06:00
tangxifan 3aeea724de [Documentation] Update for new options in fpga-verilog 2020-10-12 12:36:24 -06:00
tangxifan ccaa697e5a [Documentation] Add links to technical features to examples 2020-10-10 22:40:37 -06:00
tangxifan 56ab63d939 [Documentation] Fix format in table 2020-10-06 12:02:15 -06:00
tangxifan 113708c68f [Documentation] Reorganization the overview part by adding technical highlights 2020-10-06 11:56:10 -06:00
tangxifan 67300af987 [Documentation] Update motivation with new set of figures 2020-09-29 16:52:16 -06:00
tangxifan 639d57016b [Documentation] Update documentation about the multi-region configuration 2020-09-29 15:55:42 -06:00
tangxifan 462886fb5f [Documentation] Update documentation for the multiple region support on configuration chain 2020-09-29 14:02:03 -06:00
tangxifan 94a1324f05 [Documentation] Remove deprecated XML syntax 2020-09-26 14:31:57 -06:00
tangxifan f57fd273af [Documentation] Update documentation for smart fast configuration 2020-09-23 21:28:06 -06:00
tangxifan 3d234d840b [Documentation] Update documentation for the edge triggered attribute 2020-09-23 20:31:11 -06:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00
tangxifan ac8e937a50 [Documentation] Update for default circuit model rules 2020-08-23 14:08:38 -06:00
tangxifan fb5a5a2448 [documentation] remove the limitation on through channels 2020-08-19 20:12:49 -06:00
tangxifan 47f15729ad update doc about the limitation on using tileable routing 2020-08-19 18:37:28 -06:00
tangxifan d6d17675e2 update docoumentation about the constraints when using tileable rr_graph generator 2020-08-19 18:01:32 -06:00
tangxifan 161d660837 update documentation for the initial offset when mapping physical pins 2020-08-19 15:00:46 -06:00
tangxifan 53f87f44b4 update documentation for the multi-port support in physical pb_pin 2020-08-18 12:44:38 -06:00
tangxifan f773491f87 update documentation to sync with the new fabric bitstream format 2020-07-27 16:37:10 -06:00
tangxifan 50ac78f906 update documentation for the split fabric bitstream 2020-07-27 14:26:02 -06:00
tangxifan fcd8a3cf4d update doc format 2020-07-27 13:59:36 -06:00
tangxifan a24754611c update documentation about the 'width' syntax of fabric dependent bitstream 2020-07-27 13:56:57 -06:00
Xifan Tang aef1d7ba63 bug fix in doc about showing example fabric bitstream 2020-07-26 22:50:06 -06:00
tangxifan 872a35fc60 update doc to fix format problem; add frame_view to doc 2020-07-26 22:39:33 -06:00
tangxifan 1f39540672 update documentation about fabric bitstream file formats 2020-07-26 21:38:33 -06:00
tangxifan c3fd817bae update documentation about new XML syntax max width 2020-07-24 16:33:01 -06:00
tangxifan c26c268dcd update documentation on fast configuration support for configuration chain 2020-07-15 13:55:32 -06:00
tangxifan 862d71f57a remove obselete vpr7 XML syntax from documentation 2020-07-15 11:13:47 -06:00
tangxifan cb0df2c1c6 update doc about technology binding between circuit library and device library 2020-07-15 11:05:33 -06:00
tangxifan 65dfc545c1 update documentation for fabric key 2020-07-07 10:28:29 -06:00
tangxifan 7615db2be6 update documentation for the new fabric key rules 2020-07-06 16:44:21 -06:00
tangxifan 933801cfa7 update documentation about alias support in fabric key 2020-06-27 15:04:04 -06:00
tangxifan 8b8d92d186 update documentation for new bitstream file format 2020-06-20 18:59:45 -06:00
tangxifan 91b072d7c5 documentation update on the bitstream file format to synchronize with the latest codes 2020-06-17 11:56:40 -06:00
tangxifan ba38120093 add documentation for fabric key and reorganize command references 2020-06-12 16:15:16 -06:00
tangxifan 1a006f2ddb update documentation for separated XML files 2020-06-11 19:31:16 -06:00
tangxifan b9dd47d465 update documentation about memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan c00653961e minor format fix in documentation 2020-06-11 19:31:13 -06:00
tangxifan 0931eccbf6 update documentation for the fast configuration options 2020-06-11 19:31:13 -06:00
tangxifan fe2ba7d50a update documentation for standalone configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan de07712a3a update documentation about the frame-based configuration protocol 2020-06-11 19:31:11 -06:00
tangxifan aa77ee9af6 add tutorial for full testbench run 2020-06-11 19:31:09 -06:00
tangxifan f079c61bd3 re organize tutorials 2020-06-11 19:31:08 -06:00
tangxifan dcce782a46 update documentation about Verilog testbenches 2020-06-11 19:31:08 -06:00
tangxifan c5a3e44e61 Update Verilog fabric netlist documentation 2020-06-11 19:31:08 -06:00
tangxifan cae7fe0fed minor fix on the manual subtree 2020-06-11 19:31:08 -06:00
tangxifan c27d77a418 clean-up documentation for a shallow hierarchy 2020-06-11 19:31:08 -06:00