tangxifan
|
d2d443a988
|
start developing memory bank and standalone configuration protocol
|
2020-06-11 19:31:12 -06:00 |
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tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
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tangxifan
|
c696e3d20f
|
refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
8864920460
|
add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
10e1a4b2fe
|
format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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tangxifan
|
5a8c05378e
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
|
56e0d2a918
|
critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
|
2020-04-13 12:58:44 -06:00 |
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tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
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tangxifan
|
92a3a444f9
|
update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
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tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
|
2020-04-05 17:26:44 -06:00 |
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tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
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tangxifan
|
836f722f20
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
tangxifan
|
63306ce3a0
|
add comments to explain the memory organization in the top-level module
|
2020-04-01 11:05:30 -06:00 |
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tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
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tangxifan
|
7b9384f3b2
|
add write_gsb command to shell interface
|
2020-03-21 19:40:26 -06:00 |
|
tangxifan
|
c0e8d98c6f
|
bug fixed in tile direct builder
|
2020-03-21 12:43:56 -06:00 |
|
tangxifan
|
05ec86430a
|
temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
|
2020-03-20 17:56:03 -06:00 |
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tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |
|
tangxifan
|
5558932762
|
use sorted edges in building routing modules
|
2020-03-08 15:31:41 -06:00 |
|
tangxifan
|
f9499afe04
|
remove unused variable
|
2020-03-08 15:00:01 -06:00 |
|
tangxifan
|
0c7aa2581d
|
update vpr8 version with hotfix on undriven pins in GSB
|
2020-03-08 14:58:56 -06:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
a6c2d2c7d1
|
bug fixed for io location mapping
|
2020-02-28 14:46:01 -07:00 |
|
tangxifan
|
fdcb982903
|
adapt pnr sdc grid writer
|
2020-02-27 21:06:33 -07:00 |
|
tangxifan
|
b3796b0818
|
build io location map
|
2020-02-26 19:58:18 -07:00 |
|
tangxifan
|
8e9660b816
|
add mapped block fast look-up as placement annotation
|
2020-02-24 16:09:29 -07:00 |
|
tangxifan
|
3e07d7d5e0
|
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
|
2020-02-20 20:26:20 -07:00 |
|
tangxifan
|
85627dc128
|
put build top module online
|
2020-02-15 14:13:32 -07:00 |
|
tangxifan
|
539f13720a
|
tile direct supports inter-column/inter-row direct connections
|
2020-02-15 13:42:53 -07:00 |
|
tangxifan
|
c855ab24f5
|
put build top module memory connections online
|
2020-02-14 11:07:04 -07:00 |
|
tangxifan
|
9dc9c2c9f7
|
add build top module connection functions
|
2020-02-14 10:45:24 -07:00 |
|
tangxifan
|
36179b6ced
|
start moving top-module builder. Now adapt the utils
|
2020-02-14 10:00:24 -07:00 |
|
tangxifan
|
afe8278670
|
put routing module builder online
|
2020-02-13 17:35:29 -07:00 |
|
tangxifan
|
cf440f92d3
|
put routing module builder util function online
|
2020-02-13 16:05:23 -07:00 |
|
tangxifan
|
89086ed080
|
add verbose output to build grid module
|
2020-02-13 15:38:26 -07:00 |
|
tangxifan
|
072965cd64
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
|
tangxifan
|
59d579425e
|
add utils for duplicate pins in grid module builder
|
2020-02-12 20:48:07 -07:00 |
|
tangxifan
|
895d5b5a0a
|
add utils for grid module builder
|
2020-02-12 20:25:05 -07:00 |
|
tangxifan
|
002c2795fe
|
add memory module builder
|
2020-02-12 20:06:38 -07:00 |
|
tangxifan
|
8e381f0581
|
add wire module builder
|
2020-02-12 19:57:15 -07:00 |
|
tangxifan
|
e842150cc5
|
add lut module builder
|
2020-02-12 19:52:41 -07:00 |
|
tangxifan
|
fddd3c9463
|
add mux module builder
|
2020-02-12 19:45:14 -07:00 |
|
tangxifan
|
ea7d879b4f
|
add decoder module builder
|
2020-02-12 18:28:50 -07:00 |
|
tangxifan
|
f11832b8cf
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |