put build top module memory connections online
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tangxifan
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/********************************************************************
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* This file includes functions that are used to organize memories
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* in the top module of FPGA fabric
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "module_manager_utils.h"
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#include "build_top_module_memory.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function adds the CBX/CBY of a tile
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* to the memory modules and memory instances
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* This function is designed for organizing memory modules in top-level
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* module
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*******************************************************************/
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static
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void organize_top_module_tile_cb_modules(ModuleManager& module_manager,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const e_config_protocol_type& sram_orgz_type,
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const CircuitModelId& sram_model,
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const vtr::Matrix<size_t>& cb_instance_ids,
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const DeviceRRGSB& device_rr_gsb,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type,
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const bool& compact_routing_hierarchy) {
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/* If the CB does not exist, we can skip addition */
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if ( false == rr_gsb.is_cb_exist(cb_type)) {
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return;
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}
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/* Skip if the cb does not contain any configuration bits! */
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if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) {
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return;
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}
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vtr::Point<size_t> cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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/* If we use compact routing hierarchy, we should instanciate the unique module of SB */
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, vtr::Point<size_t>(rr_gsb.get_x(), rr_gsb.get_y()));
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cb_coord.set_x(unique_mirror.get_cb_x(cb_type));
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cb_coord.set_y(unique_mirror.get_cb_y(cb_type));
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}
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std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coord);
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ModuleId cb_module = module_manager.find_module(cb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Identify if this sub module includes configuration bits,
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* we will update the memory module and instance list
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*/
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if (0 < find_module_num_config_bits(module_manager, cb_module,
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circuit_lib, sram_model,
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sram_orgz_type)) {
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/* Note that use the original CB coodinate for instance id searching ! */
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module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)]);
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}
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}
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/********************************************************************
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* This function adds the SB, CBX, CBY and Grid of a tile
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* to the memory modules and memory instances
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* This function is designed for organizing memory modules in top-level
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* module
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*******************************************************************/
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static
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void organize_top_module_tile_memory_modules(ModuleManager& module_manager,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const e_config_protocol_type& sram_orgz_type,
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const CircuitModelId& sram_model,
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const DeviceGrid& grids,
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const vtr::Matrix<size_t>& grid_instance_ids,
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const DeviceRRGSB& device_rr_gsb,
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const vtr::Matrix<size_t>& sb_instance_ids,
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const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
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const bool& compact_routing_hierarchy,
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const vtr::Point<size_t>& tile_coord,
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const e_side& tile_border_side) {
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vtr::Point<size_t> gsb_coord_range = device_rr_gsb.get_gsb_range();
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vtr::Point<size_t> gsb_coord(tile_coord.x(), tile_coord.y() - 1);
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/* We do NOT consider SB and CBs if the gsb is not in the range! */
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if ( (gsb_coord.x() < gsb_coord_range.x())
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&& (gsb_coord.y() < gsb_coord_range.y()) ) {
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(gsb_coord.x(), gsb_coord.y());
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/* Find Switch Block: unique module id and instance id!
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* Note that switch block does always exist in a GSB
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*/
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vtr::Point<size_t> sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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/* If we use compact routing hierarchy, we should instanciate the unique module of SB */
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if (true == compact_routing_hierarchy) {
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
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sb_coord.set_x(unique_mirror.get_sb_x());
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sb_coord.set_y(unique_mirror.get_sb_y());
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}
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std::string sb_module_name = generate_switch_block_module_name(sb_coord);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Identify if this sub module includes configuration bits,
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* we will update the memory module and instance list
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*/
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/* If the CB does not exist, we can skip addition */
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if ( true == rr_gsb.is_sb_exist()) {
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if (0 < find_module_num_config_bits(module_manager, sb_module,
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circuit_lib, sram_model,
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sram_orgz_type)) {
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module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()]);
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}
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}
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/* Try to find and add CBX and CBY */
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organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
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sram_orgz_type, sram_model,
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cb_instance_ids.at(CHANX),
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device_rr_gsb, rr_gsb, CHANX,
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compact_routing_hierarchy);
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organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
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sram_orgz_type, sram_model,
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cb_instance_ids.at(CHANY),
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device_rr_gsb, rr_gsb, CHANY,
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compact_routing_hierarchy);
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}
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/* Find the module name for this type of grid */
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t_physical_tile_type_ptr grid_type = grids[tile_coord.x()][tile_coord.y()].type;
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/* Skip EMPTY Grid */
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if (true == is_empty_type(grid_type)) {
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return;
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}
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/* Skip width > 1 or height > 1 Grid, which should already been processed when offset=0 */
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if ( (0 < grids[tile_coord.x()][tile_coord.y()].width_offset)
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|| (0 < grids[tile_coord.x()][tile_coord.y()].height_offset) ) {
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return;
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}
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), tile_border_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Identify if this sub module includes configuration bits,
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* we will update the memory module and instance list
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*/
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if (0 < find_module_num_config_bits(module_manager, grid_module,
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circuit_lib, sram_model,
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sram_orgz_type)) {
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module_manager.add_configurable_child(top_module, grid_module, grid_instance_ids[tile_coord.x()][tile_coord.y()]);
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}
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}
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/********************************************************************
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* Organize the list of memory modules and instances
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* This function will record all the sub modules of the top-level module
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* (those have memory ports) to two lists:
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* 1. memory_modules records the module ids
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* 2. memory_instances records the instance ids
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* To keep a clean memory connection between sub modules and top-level module,
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* the sequence of memory_modules and memory_instances will follow
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* a chain of tiles considering their physical location
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*
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* Inter tile connection:
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* +--------------------------------------------------------+
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* | +------+------+-----+------+ |
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* | | I/O | I/O | ... | I/O | |
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* | | TOP | TOP | | TOP | |
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* | +------+------+-----+------+ |
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* | +---------------------------------->tail |
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* | +------+ | +------+------+-----+------+ +------+ |
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* | | | | | | | | | | | |
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* | | I/O | | | Tile | Tile | ... | Tile | | I/O | |
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* | | LEFT | | | [h+1]| [h+2]| | [n] | |RIGHT | |
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* | +------+ | +------+------+-----+------+ +------+ |
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* | +-------------------------------+ |
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* | ... ... ... ... ... | ... |
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* | +-------------------------------+ |
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* | +------+ | +------+------+-----+------+ +------+ |
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* | | | | | | | | | | | |
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* | | I/O | | | Tile | Tile | ... | Tile | | I/O | |
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* | | LEFT | | | [i+1]| [i+2]| | [j] | |RIGHT | |
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* | +------+ | +------+------+-----+------+ +------+ |
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* | +-------------------------------+ |
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* | +------+ +------+------+-----+------+ | +------+ |
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* | | | | | | | | | | | |
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* | | I/O | | Tile | Tile | ... | Tile | | | I/O | |
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* | | LEFT | | [0] | [1] | | [i] | | |RIGHT | |
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* | +------+ +------+------+-----+------+ | +------+ |
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* +-------------------------------------------+ |
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* +------+------+-----+------+ |
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* | I/O | I/O | ... | I/O | |
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* |BOTTOM|BOTTOM| |BOTTOM| |
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* +------+------+-----+------+ |
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* head >-----------------------------------------------+
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*
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* Inner tile connection
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*
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* Tile
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* +---------------+----------+
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* <-+---------------+ + |
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* | | | |
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* | CLB | | CBY |
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* | +-|-+ |
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* | | | |
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* +---------------+----------+
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* | +-+----+-----+---<---
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* | CBX | SB |
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* | | |
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* +---------------+----------+
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*
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*******************************************************************/
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void organize_top_module_memory_modules(ModuleManager& module_manager,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const e_config_protocol_type& sram_orgz_type,
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const CircuitModelId& sram_model,
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const DeviceGrid& grids,
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const vtr::Matrix<size_t>& grid_instance_ids,
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const DeviceRRGSB& device_rr_gsb,
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const vtr::Matrix<size_t>& sb_instance_ids,
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const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
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const bool& compact_routing_hierarchy) {
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/* Ensure clean vectors to return */
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VTR_ASSERT(true == module_manager.configurable_children(top_module).empty());
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/* First, organize the I/O tiles on the border */
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/* Special for the I/O tileas on RIGHT and BOTTOM,
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* which are only I/O blocks, which do NOT contain CBs and SBs
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*/
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std::vector<e_side> io_sides{BOTTOM, RIGHT, TOP, LEFT};
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std::map<e_side, std::vector<vtr::Point<size_t>>> io_coords;
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/* BOTTOM side I/Os */
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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io_coords[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
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}
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/* RIGHT side I/Os */
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for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
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io_coords[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
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}
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/* TOP side I/Os
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* Special case for TOP side: We need tile at ix = 0, which has a SB!!!
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*
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* TOP-LEFT CORNER of FPGA fabric
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*
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* +--------+ +-------+
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* | EMPTY | | EMPTY |
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* | Grid | | CBX |
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* | [0][x] | | |
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* +--------+ +-------+
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* +--------+ +--------+
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* | EMPTY | | SB |
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* | CBX | | [0][x] |
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* +--------+ +--------+
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*
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*/
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for (size_t ix = grids.width() - 2; ix >= 1; --ix) {
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io_coords[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
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}
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io_coords[TOP].push_back(vtr::Point<size_t>(0, grids.height() - 1));
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/* LEFT side I/Os */
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for (size_t iy = grids.height() - 2; iy >= 1; --iy) {
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io_coords[LEFT].push_back(vtr::Point<size_t>(0, iy));
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}
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for (const e_side& io_side : io_sides) {
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for (const vtr::Point<size_t>& io_coord : io_coords[io_side]) {
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/* Identify the GSB that surrounds the grid */
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organize_top_module_tile_memory_modules(module_manager, top_module,
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circuit_lib, sram_orgz_type, sram_model,
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grids, grid_instance_ids,
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device_rr_gsb, sb_instance_ids, cb_instance_ids,
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compact_routing_hierarchy,
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io_coord, io_side);
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}
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}
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/* For the core grids */
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std::vector<vtr::Point<size_t>> core_coords;
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bool positive_direction = true;
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for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
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/* For positive direction: -----> */
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if (true == positive_direction) {
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for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
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core_coords.push_back(vtr::Point<size_t>(ix, iy));
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}
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} else {
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VTR_ASSERT(false == positive_direction);
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/* For negative direction: -----> */
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for (size_t ix = grids.width() - 2; ix >= 1; --ix) {
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core_coords.push_back(vtr::Point<size_t>(ix, iy));
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}
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}
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/* Flip the positive direction to be negative */
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positive_direction = !positive_direction;
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}
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for (const vtr::Point<size_t>& core_coord : core_coords) {
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organize_top_module_tile_memory_modules(module_manager, top_module,
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circuit_lib, sram_orgz_type, sram_model,
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grids, grid_instance_ids,
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device_rr_gsb, sb_instance_ids, cb_instance_ids,
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compact_routing_hierarchy,
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core_coord, NUM_SIDES);
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}
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}
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/*********************************************************************
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* Add the port-to-port connection between all the memory modules
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* and their parent module
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*
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* Create nets to wire the control signals of memory module to
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* the configuration ports of primitive module
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*
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* Configuration Chain
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* -------------------
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*
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* config_bus (head) config_bus (tail)
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* | ^
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* primitive | |
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* +---------------------------------------------+
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* | | | |
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* | v | |
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* | +-------------------------------------+ |
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* | | CMOS-based Memory Modules | |
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* | +-------------------------------------+ |
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* | | | |
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* | v v |
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* | sram_out sram_outb |
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* | |
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* +---------------------------------------------+
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*
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* Memory bank
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* -----------
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*
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* config_bus (BL) config_bus (WL)
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* | |
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* primitive | |
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* +---------------------------------------------+
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* | | | |
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* | v v |
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* | +-------------------------------------+ |
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* | | CMOS-based Memory Modules | |
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* | +-------------------------------------+ |
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* | | | |
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* | v v |
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* | sram_out sram_outb |
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* | |
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* +---------------------------------------------+
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*
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**********************************************************************/
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static
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void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type) {
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switch (sram_orgz_type) {
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case CONFIG_MEM_STANDALONE:
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/* Nothing to do */
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break;
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case CONFIG_MEM_SCAN_CHAIN: {
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add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, CONFIG_MEM_SCAN_CHAIN);
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break;
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}
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case CONFIG_MEM_MEMORY_BANK:
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/* TODO: */
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid type of SRAM organization!\n");
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exit(1);
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}
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}
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/********************************************************************
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* TODO:
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* Add the port-to-port connection between a memory module
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* and the configuration bus of a primitive module
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*
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* Create nets to wire the control signals of memory module to
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* the configuration ports of primitive module
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*
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* Primitive module
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* +----------------------------+
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* | +--------+ |
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* config | | | |
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* ports --->|--------------->| Memory | |
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* | | Module | |
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* | | | |
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* | +--------+ |
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* +----------------------------+
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* The detailed config ports really depend on the type
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* of SRAM organization.
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*
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* The config_bus in the argument is the reserved address of configuration
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* bus in the parent_module for this memory module
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*
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* The configuration bus connection will depend not only
|
||||
* the design technology of the memory cells but also the
|
||||
* configuration styles of FPGA fabric.
|
||||
* Here we will branch on the design technology
|
||||
*
|
||||
* Note: this function SHOULD be called after the pb_type_module is created
|
||||
* and its child module (logic_module and memory_module) is created!
|
||||
*******************************************************************/
|
||||
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
|
||||
const ModuleId& parent_module,
|
||||
const e_config_protocol_type& sram_orgz_type,
|
||||
const e_circuit_model_design_tech& mem_tech) {
|
||||
switch (mem_tech) {
|
||||
case CIRCUIT_MODEL_DESIGN_CMOS:
|
||||
add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module,
|
||||
sram_orgz_type);
|
||||
break;
|
||||
case CIRCUIT_MODEL_DESIGN_RRAM:
|
||||
/* TODO: */
|
||||
break;
|
||||
default:
|
||||
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||
"Invalid type of memory design technology!\n");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#ifndef BUILD_TOP_MODULE_MEMORY_H
|
||||
#define BUILD_TOP_MODULE_MEMORY_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
|
||||
#include <vector>
|
||||
#include <map>
|
||||
#include "vtr_ndmatrix.h"
|
||||
#include "module_manager.h"
|
||||
#include "circuit_types.h"
|
||||
#include "circuit_library.h"
|
||||
#include "device_grid.h"
|
||||
#include "device_rr_gsb.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void organize_top_module_memory_modules(ModuleManager& module_manager,
|
||||
const ModuleId& top_module,
|
||||
const CircuitLibrary& circuit_lib,
|
||||
const e_config_protocol_type& sram_orgz_type,
|
||||
const CircuitModelId& sram_model,
|
||||
const DeviceGrid& grids,
|
||||
const vtr::Matrix<size_t>& grid_instance_ids,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const vtr::Matrix<size_t>& sb_instance_ids,
|
||||
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
|
||||
const bool& compact_routing_hierarchy);
|
||||
|
||||
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
|
||||
const ModuleId& parent_module,
|
||||
const e_config_protocol_type& sram_orgz_type,
|
||||
const e_circuit_model_design_tech& mem_tech);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
|
|
@ -10,6 +10,9 @@
|
|||
#include "vtr_log.h"
|
||||
#include "vtr_assert.h"
|
||||
|
||||
/* Headers from openfpgautil library */
|
||||
#include "openfpga_port.h"
|
||||
|
||||
#include "openfpga_naming.h"
|
||||
#include "memory_utils.h"
|
||||
#include "pb_type_utils.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue