tangxifan
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a4c266d59a
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[Arch] Add pack patterns for soft adders; Still fail in packing
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2021-02-03 19:11:15 -07:00 |
Ganesh Gore
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6cdc31f073
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[Flow] ACE is optional duign flow script
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2021-02-03 19:07:48 -07:00 |
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tangxifan
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fb10a96ee5
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Merge pull request #214 from lnis-uofu/gg_cleanup
[Cleanup] Removed deadcode
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2021-02-03 12:44:00 -07:00 |
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tangxifan
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cac1160bf7
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[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
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2021-02-03 11:20:56 -07:00 |
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Ganesh Gore
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df4a397470
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[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
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tangxifan
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4c825b27b3
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[Benchmark] Change to use adder lut4 to be consistent with architecture
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2021-02-03 09:37:48 -07:00 |
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tangxifan
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31441c0b64
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[Test] Deploy adder_8 to soft adder test
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2021-02-03 09:26:38 -07:00 |
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tangxifan
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05d63567d0
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[Benchmark] Use latest adder eblif file
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2021-02-03 09:21:38 -07:00 |
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tangxifan
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f124c79e6b
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Merge pull request #213 from lnis-uofu/bump_yosys_adder
Bumping up latest yosys changes related to adder tech mapping
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2021-02-03 09:15:43 -07:00 |
Lalit Sharma
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ebe66dea35
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Bumping up latest yosys changes related to adder tech mapping
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2021-02-03 14:30:06 +05:30 |
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tangxifan
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2c06960e4f
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[Benchmark] Add subckt definition to micro benchmark and2.eblif
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2021-02-02 15:51:16 -07:00 |
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tangxifan
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021520783b
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[Arch] Add dummy timing info to adder_lut4 and carry_follower model
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2021-02-02 15:49:43 -07:00 |
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tangxifan
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dc320182b0
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[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
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2021-02-02 15:04:43 -07:00 |
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tangxifan
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8e36ed1ab6
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[Test] Update task configuration to use and2 eblif
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2021-02-02 15:01:15 -07:00 |
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tangxifan
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62803dc044
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[Benchmark] Add eblif example for and2 benchmark
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2021-02-02 14:59:31 -07:00 |
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tangxifan
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5e2847bc41
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[Test] Update test case to use eblif file
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2021-02-02 09:33:41 -07:00 |
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tangxifan
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39e6f62d91
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[Benchmark] Use eblif in naming the adder_8 micro benchmark
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2021-02-02 09:32:42 -07:00 |
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tangxifan
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d3397f6936
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[Script] Remove activity from bitstream setting example script
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2021-02-02 09:25:36 -07:00 |
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tangxifan
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9ff5e7926b
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[Test] Update test case to use the adder benchmark
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2021-02-02 09:24:39 -07:00 |
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tangxifan
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7f14dfbe87
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[Script] Add example script to use bitstream setting
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2021-02-02 09:18:08 -07:00 |
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tangxifan
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d83158654c
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[Doc] Add a draft documentation about the bitstream setting
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2021-02-01 22:33:17 -07:00 |
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tangxifan
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0c409b5bcc
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[Tool] Add bitstream annotation support
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2021-02-01 20:49:36 -07:00 |
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tangxifan
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faabdab815
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[Tool] Remove redundant tab in bitstream setting writer
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2021-02-01 18:04:21 -07:00 |
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tangxifan
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d5b1cc5ec7
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[Tool] Bug fix in parser for bitstream settings
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2021-02-01 18:01:42 -07:00 |
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tangxifan
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f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
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04594cb7ab
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[Test] Adapt bitstream annotatin file to parser's requirement
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2021-02-01 17:38:36 -07:00 |
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tangxifan
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280c9620aa
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[Test] Add an example bitstream annotation file
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2021-02-01 16:01:21 -07:00 |
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tangxifan
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a6354fab7c
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[Arch] Decide to move external bitstream definition to a separated XML file
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2021-02-01 15:57:44 -07:00 |
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tangxifan
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df88e2adc0
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[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
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2021-02-01 14:26:11 -07:00 |
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tangxifan
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10302752a7
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[Arch] Bug fix in architecture. Now soft adder modes are accepted
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2021-02-01 13:43:39 -07:00 |
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tangxifan
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d8927e12e8
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[Arch] Add soft adder operating mode to test architecture
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2021-02-01 12:25:37 -07:00 |
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tangxifan
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7f0f7a1c70
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[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
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2021-02-01 12:05:04 -07:00 |
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tangxifan
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b215b868c1
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[HDL] Bug fix in HDL netlist due to port name mismatching
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2021-02-01 11:35:25 -07:00 |
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tangxifan
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e4abe263c3
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[Arch] Bug fix
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2021-02-01 11:29:27 -07:00 |
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tangxifan
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fb05e1a938
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[Arch] bug fix due to using openfpga cell library
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2021-02-01 11:27:21 -07:00 |
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tangxifan
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940dce469a
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[Test] Bug fix for test case configuration
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2021-02-01 11:19:47 -07:00 |
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tangxifan
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a80acfb547
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[Test] Add new test case to CI script
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2021-02-01 11:16:12 -07:00 |
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tangxifan
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af630dab1e
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[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
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2021-02-01 10:53:38 -07:00 |
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tangxifan
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9cce411eda
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[Test] Add adder test cases
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2021-02-01 10:42:24 -07:00 |
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tangxifan
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0eb949b85a
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[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
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2021-02-01 10:34:32 -07:00 |
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tangxifan
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e0e2506e32
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[HDL] Remove redundant comments
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2021-02-01 10:33:08 -07:00 |
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tangxifan
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39543f7945
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[HDL] Add carry mux2 to cell library
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2021-02-01 10:23:46 -07:00 |
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tangxifan
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6ede799c16
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[Arch] Add openfpga architecture for the QLSOFA
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2021-02-01 10:15:35 -07:00 |
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tangxifan
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f51aaae4a2
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Merge pull request #208 from lnis-uofu/bump_yosys
Bumping up yosys submodule as an option (-verilog) is added to write …
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2021-02-01 10:07:25 -07:00 |
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tangxifan
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df05911d24
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Merge branch 'master' into soft_adder_lut_support
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2021-02-01 10:02:05 -07:00 |
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Lalit Sharma
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0f287fb539
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Bumping up yosys submodule as an option (-verilog) is added to write verilog file
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2021-02-01 13:43:31 +05:30 |
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ganeshgore
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186a0cadfb
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Checking complete flow of build.yml from non master branch (#207)
* [CICD] SHA extraction bug fix
* [CICD] Docker image builds but push from master
* [CICD] General cleanup
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2021-01-30 09:40:53 -07:00 |
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tangxifan
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20aebebcf2
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Merge pull request #206 from lnis-uofu/gg_ci_cd_dev
[CICD] Added SHA tag to docker build image
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2021-01-29 22:11:28 -07:00 |
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ganeshgore
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d41ca7d2fd
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Merge pull request #203 from lnis-uofu/dev
Remove the hard requirement on signal activity file
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2021-01-29 21:29:01 -07:00 |
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Ganesh Gore
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52dc76c25e
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[CICD] Added SHA tag to docker build image
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2021-01-29 20:22:45 -07:00 |