tangxifan
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8267dad8ef
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add decoder support for Z signals
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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c85ccceac7
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try bug fixing in memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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e14c39e14c
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update Verilog full testbench generation to support memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
|
ad7422359d
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deploy compact constant values in Verilog codes
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2020-06-11 19:31:13 -06:00 |
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tangxifan
|
8ec8ac4118
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bug fixed in flatten memory organization. Passed verification
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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fbe05963e0
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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d2d443a988
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start developing memory bank and standalone configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
9e176b8d38
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add fast configuration stats to log
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b5e5182f52
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frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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31c9a011dd
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keep bug fixing for arch decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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bdc9efb38f
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bug fix in top-level testbench for frame-based decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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986956e474
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bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
6a72c66eb8
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bug fixed for frame-based configuration memory in top-level full testbench
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
8aa665b3b2
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bug fix in the Verilog codes for frame decoders
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
bf9f62f0f7
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keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
ece651ade2
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bug fixed in the configuration chian errrors
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
85921dcc05
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add fabric bitstream builder for frame-based configuration protocol
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
8c14cced84
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start improve fabric bitstream database to support frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
5c5a044c68
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
8915d10d27
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add verbose output option to configure port disable timing writer
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2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
6177921d4c
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bug fixed in configure port disable timing. Now we disable the right ports of LUTs
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
e9ceedb01b
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use constant openfpga context in SDC generator
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2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
067d09f954
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bug fix for configure port disable_timing writer
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
ae9f1fbd90
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critical bug fixed in the disable MUX output
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
99751b84f5
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bug fix in configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
02e86c565a
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bug fix in configuration chain SDC writer
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
4c0953415b
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add configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
|
dad99d13a2
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bug fixed in SDC timing writer for primitive pb_type
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
8d2360a710
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simplify include_netlist.v
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2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b8a79c563d
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bug fix in the SDC port generation
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2020-06-11 19:31:05 -06:00 |