tangxifan
|
189c94ff19
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[Test] Deploy new mac benchmarks to tests
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2021-04-23 20:44:14 -06:00 |
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tangxifan
|
200b6d39a6
|
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
|
2021-04-23 20:36:28 -06:00 |
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tangxifan
|
671394ec2c
|
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
|
2021-04-23 20:33:43 -06:00 |
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tangxifan
|
cbb7d41b6e
|
[Script] Enable constant net routing for VTR benchmarks
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2021-04-23 14:15:13 -06:00 |
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tangxifan
|
784713e88a
|
[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
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tangxifan
|
a16896054d
|
[Script] Enable constant net routing for iwls benchmarks
|
2021-04-22 19:16:32 -06:00 |
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tangxifan
|
1dcb8e39a9
|
[Test] Unlock more IWLS'2005 benchmarks in testing
|
2021-04-22 09:23:33 -06:00 |
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tangxifan
|
61a473e479
|
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
|
2021-04-21 22:56:19 -06:00 |
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tangxifan
|
5a519390ff
|
[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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tangxifan
|
ce6018e123
|
[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
|
adfea88be2
|
[HDL] Rename multi-mode DFF module
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2021-04-21 20:06:03 -06:00 |
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tangxifan
|
62497549b6
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[HDL] Add multi-mode DFF module
|
2021-04-21 20:04:40 -06:00 |
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tangxifan
|
3a5c26c6a1
|
[Test] Update IWLS test by using new architecture and customize DFF techmap
|
2021-04-21 19:51:25 -06:00 |
|
tangxifan
|
8cbea6a268
|
[HDL] Add technology library for customizable DFF synthesis
|
2021-04-21 19:50:51 -06:00 |
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tangxifan
|
3d615e1516
|
[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
|
2021-04-21 19:50:07 -06:00 |
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tangxifan
|
9d9840d9b7
|
[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
|
8046b16c15
|
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
|
2021-04-21 14:04:34 -06:00 |
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tangxifan
|
b203ef7bc2
|
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
|
2021-04-21 14:03:51 -06:00 |
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tangxifan
|
2fa370d7d5
|
[Test] Patch regression tests for fpga bitstream
|
2021-04-19 17:15:14 -06:00 |
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tangxifan
|
64163edbe6
|
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
|
2021-04-19 16:15:25 -06:00 |
|
tangxifan
|
578d81b67a
|
[Test] Patch task configuration file
|
2021-04-19 16:15:00 -06:00 |
|
tangxifan
|
18eb5c9de9
|
[Test] Deploy new test to CI
|
2021-04-19 15:56:41 -06:00 |
|
tangxifan
|
5976cc0a1c
|
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
|
2021-04-19 15:54:18 -06:00 |
|
tangxifan
|
7018073e28
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
tangxifan
|
da95da933b
|
[Test] Add pin constraint file to map reset to correct FPGA pins
|
2021-04-17 15:04:26 -06:00 |
|
tangxifan
|
e3dafe99da
|
[Arch] Revert to old version arch due to editing by mistake
|
2021-04-16 20:58:32 -06:00 |
|
tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
|
2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
7172fc9ea1
|
[Test] Patch test for architecture using asynchronous DFFs
|
2021-04-16 20:48:37 -06:00 |
|
tangxifan
|
0a15f366cb
|
[HDL] Patch dff models used in yosys tech map
|
2021-04-16 20:48:15 -06:00 |
|
tangxifan
|
16e02ef485
|
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
|
2021-04-16 20:47:39 -06:00 |
|
tangxifan
|
1c2f91b7e6
|
[Script] Patch yosys script with dff tech map
|
2021-04-16 20:47:18 -06:00 |
|
tangxifan
|
2666726f36
|
[Script] Remove clock routing from example openfpga shell script without ace
|
2021-04-16 20:46:49 -06:00 |
|
tangxifan
|
23d08757cf
|
[Script] Add example script without using ACE2
|
2021-04-16 20:20:10 -06:00 |
|
tangxifan
|
bbdc0e53af
|
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
|
2021-04-16 20:14:48 -06:00 |
|
tangxifan
|
b11d03f9c5
|
[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
|
tangxifan
|
93be81abe1
|
[Test] Add test case for architecture using DFF with reset
|
2021-04-16 20:00:48 -06:00 |
|
tangxifan
|
5414a6a3da
|
[Script] Add yosys script with custom DFF tech mapping
|
2021-04-16 20:00:30 -06:00 |
|
tangxifan
|
4239bb4e68
|
[Arch] Patch architecture files using multi-mode DFFs
|
2021-04-16 19:59:55 -06:00 |
|
tangxifan
|
f2f7f010ea
|
[Arch] Add new architectures using DFF with reset in VPR
|
2021-04-16 19:26:18 -06:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |
|
tangxifan
|
ff4460695b
|
[HDL] Add dff tech map files for yosys
|
2021-04-16 17:00:55 -06:00 |
|
tangxifan
|
e46c6e75a3
|
[Benchmark] Add missing RTL for IWLS2005 benchmarks
|
2021-04-16 16:50:41 -06:00 |
|
tangxifan
|
87587bbb74
|
[Test] Add iwls2005 benchmarks to regression tests
|
2021-04-16 16:12:05 -06:00 |
|
tangxifan
|
1566a5558a
|
[Test] Add task configuration file for iwls2005
|
2021-04-16 16:10:31 -06:00 |
|
tangxifan
|
43bf016576
|
[Script] Add example openfpga shell script for iwls benchmark
|
2021-04-16 16:09:47 -06:00 |
|
tangxifan
|
26d3b5a954
|
[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
|
2021-04-16 16:08:58 -06:00 |
|
tangxifan
|
86ad572530
|
[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
|
2021-04-16 14:27:54 -06:00 |
|
tangxifan
|
b469705819
|
Merge branch 'master' into fpga_sdc_test
|
2021-04-11 21:14:46 -06:00 |
|
tangxifan
|
1db8bd7eec
|
[Test] Update regression test with new SDC tests
|
2021-04-11 20:24:32 -06:00 |
|
tangxifan
|
07f6066c11
|
[Script] Update timing unit in SDC example script
|
2021-04-11 20:24:18 -06:00 |
|
tangxifan
|
94c4c817eb
|
[Test] Expand sdc time unit test to sweep all the available units
|
2021-04-11 20:14:09 -06:00 |
|
tangxifan
|
a4893e27cf
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
tangxifan
|
44d97ead86
|
Merge branch 'master' into hetergeneous_arch
|
2021-03-23 17:05:03 -06:00 |
|
tangxifan
|
b00b4f0f5f
|
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
|
2021-03-23 15:44:53 -06:00 |
|
tangxifan
|
d82ffe0cbf
|
[Test] Deploy MAC_8 benchmark to regression test
|
2021-03-23 15:36:28 -06:00 |
|
tangxifan
|
108c84a022
|
[HDL] Add HDL for 8-bit single-mode multiplier
|
2021-03-23 15:36:09 -06:00 |
|
tangxifan
|
145a80de43
|
[Script] Add an openfpga shell script for heterogeneous fpga verification
|
2021-03-23 15:35:34 -06:00 |
|
tangxifan
|
fdec72b5bc
|
[Arch] Add an example architecture with 8-bit single-mode multiplier
|
2021-03-23 15:35:06 -06:00 |
|
tangxifan
|
be03eafd66
|
[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
|
2021-03-23 15:33:37 -06:00 |
|
tangxifan
|
8c970a792a
|
[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
|
2021-03-23 15:33:00 -06:00 |
|
tangxifan
|
6b0409da60
|
[Script] Add a template yosys script support only DSP mapping
|
2021-03-23 15:32:10 -06:00 |
|
tangxifan
|
a4bbffd1aa
|
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
|
2021-03-23 15:30:41 -06:00 |
|
tangxifan
|
fff16a01ab
|
[Test] Update tolerance when checking VTR benchmark QoR
|
2021-03-23 12:27:20 -06:00 |
|
tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
|
2021-03-23 12:26:33 -06:00 |
|
tangxifan
|
e3f8a6cf7a
|
[Test] Deploy QoR check to VTR benchmark regression test
|
2021-03-23 11:15:22 -06:00 |
|
tangxifan
|
351dec5935
|
[Test] Add QoR csv file for vtr benchmarks
|
2021-03-23 11:15:02 -06:00 |
|
tangxifan
|
23e7f7f1f5
|
[Script] Update default list of result extraction for openfpga flow
|
2021-03-23 11:06:42 -06:00 |
|
tangxifan
|
adfbd28a7a
|
[Script] Add a simple QoR checker
|
2021-03-23 11:06:16 -06:00 |
|
tangxifan
|
61eddb08de
|
[Test] Update task configuration by commenting out high-runtime VTR benchmarks
|
2021-03-22 14:42:42 -06:00 |
|
tangxifan
|
55d1004cf2
|
[Benchmark] Add missing DPRAM module to LU32PEEng
|
2021-03-22 14:41:38 -06:00 |
|
tangxifan
|
5fc83ebea3
|
[Benchmark] Add missing DPRAM modules to LU8PEEng
|
2021-03-22 14:38:00 -06:00 |
|
tangxifan
|
b828f91a78
|
[Benchmark] Add missing DPRAM and SPRAM modules to mcml
|
2021-03-22 14:13:05 -06:00 |
|
tangxifan
|
d050f1b746
|
[Script] Enable fast bitstream generation for VTR benchmarks
|
2021-03-22 12:54:36 -06:00 |
|
tangxifan
|
4bfd0c0a02
|
[Test] Enable more VTR benchmark in testing
|
2021-03-22 12:53:30 -06:00 |
|
tangxifan
|
b906ab814e
|
[Benchmark] Add missing DPRAM module to mkPktMerge
|
2021-03-22 12:51:23 -06:00 |
|
tangxifan
|
310c2a9495
|
[Benchmark] Add missing DPRAM module to mkDelayWorker32B
|
2021-03-22 12:51:02 -06:00 |
|
tangxifan
|
707247283c
|
[Benchmark] Add missing DPRAM module to mkSMAdapter4B
|
2021-03-22 12:50:39 -06:00 |
|
tangxifan
|
eb056e2afd
|
[Benchmark] Add missing DPRAM module to or1200
|
2021-03-22 12:50:17 -06:00 |
|
tangxifan
|
7fd345a616
|
[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
|
2021-03-22 10:39:47 -06:00 |
|
tangxifan
|
cc10b10703
|
[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
|
2021-03-20 22:53:37 -06:00 |
|
tangxifan
|
169ee53b79
|
[Benchmark] Add missing modules to VTR benchmarks
|
2021-03-20 22:53:17 -06:00 |
|
tangxifan
|
eca2a35612
|
[Script] Add route chan width option to vtr openfpga script
|
2021-03-20 22:00:09 -06:00 |
|
tangxifan
|
9a3aff274f
|
[Test] Use fix routing channel width to save runtime for VTR benchmarks
|
2021-03-20 21:59:44 -06:00 |
|
tangxifan
|
ca9a70fc88
|
[Test] Comment out benchmarks have problems in synthesis
|
2021-03-20 21:29:21 -06:00 |
|
tangxifan
|
125e94a6b3
|
[Test] Add full VTR benchmark (with most commented); ready for massive testing
|
2021-03-20 21:01:18 -06:00 |
|
tangxifan
|
2bd8ef2af9
|
[Benchmark] Patch boundtop.v with missing SPRAM module
|
2021-03-20 21:00:53 -06:00 |
|
tangxifan
|
cb07848475
|
[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
|
2021-03-20 18:11:54 -06:00 |
|
tangxifan
|
f3792bc6f6
|
[Test] Update VTR benchmark test case to include DSP example benchmark
|
2021-03-20 18:09:19 -06:00 |
|
tangxifan
|
477a522885
|
[HDL] Rename tech lib to be consistent with arch name changes
|
2021-03-20 18:08:03 -06:00 |
|
tangxifan
|
911979a731
|
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
|
2021-03-20 18:04:59 -06:00 |
|
tangxifan
|
1185f7b8bf
|
[Script] Add a template yosys script to enable DSP mapping
|
2021-03-20 17:05:30 -06:00 |
|
tangxifan
|
6bf4880c50
|
[benchmark] Add vtr benchmark
|
2021-03-17 15:24:26 -06:00 |
|
tangxifan
|
f9dc7c1b54
|
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
|
2021-03-17 15:15:22 -06:00 |
|
tangxifan
|
08a86e056a
|
[Test] Add vtr benchmark regression test
|
2021-03-17 15:13:58 -06:00 |
|
tangxifan
|
7eeb35d21f
|
[Script] Bug fix in yosys script to synthesis BRAM
|
2021-03-17 15:12:04 -06:00 |
|
tangxifan
|
1976a8068f
|
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
|
2021-03-17 15:11:17 -06:00 |
|
tangxifan
|
deee7ba366
|
[Script] Add example script to run vtr benchmarks
|
2021-03-17 15:10:56 -06:00 |
|
tangxifan
|
910f8471dd
|
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
|
2021-03-17 15:10:05 -06:00 |
|
tangxifan
|
76113a80fa
|
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
|
2021-03-17 15:09:12 -06:00 |
|
tangxifan
|
e1f8b252b1
|
Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-16 20:05:21 -06:00 |