tangxifan
|
853883cd36
|
[core] code format
|
2024-07-30 12:56:03 -07:00 |
|
tangxifan
|
234eee19ae
|
[core] revert
|
2024-07-30 12:29:32 -07:00 |
|
tangxifan
|
1513ea749b
|
[core] supporting clk spine on the same direction
|
2024-07-16 22:12:51 -07:00 |
|
tangxifan
|
18d12109fb
|
[core] fixed a critical bug where cb port name using index is not considered on clock network entry
|
2024-07-16 17:42:21 -07:00 |
|
tangxifan
|
c1f46c448a
|
[core] fixed a critical bug where clock network entry is on a CHANY
|
2024-07-16 17:04:44 -07:00 |
|
tangxifan
|
cbd10e1222
|
[core] fixed a bug where tile module's global port is not derived from dedicated clock network
|
2024-07-16 16:58:21 -07:00 |
|
tangxifan
|
f607987386
|
[core] patch the out-of-range in clock rr nodes
|
2024-07-16 16:45:55 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
215de8eb93
|
[core] code format
|
2024-07-10 14:17:22 -07:00 |
|
tangxifan
|
f5ba43e392
|
[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
|
2024-07-10 14:16:24 -07:00 |
|
tangxifan
|
213914e4ac
|
[core] code format
|
2024-07-10 12:23:57 -07:00 |
|
tangxifan
|
48e159dd8d
|
[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
|
2024-07-10 12:23:15 -07:00 |
|
tangxifan
|
c6dd33a965
|
[core] fixed a bug when annotating global nets on OPIN
|
2024-07-10 11:59:25 -07:00 |
|
tangxifan
|
96bdcc8b35
|
[core] code format
|
2024-07-09 22:54:55 -07:00 |
|
tangxifan
|
27e29f949c
|
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
|
2024-07-09 22:53:12 -07:00 |
|
tangxifan
|
092b8b038f
|
[core] remove verbose out
|
2024-07-08 22:23:37 -07:00 |
|
tangxifan
|
04504e4d5d
|
[core] code format
|
2024-07-08 22:22:59 -07:00 |
|
tangxifan
|
1cdb1c5995
|
[core] fixed a bug on calculating subtile pins
|
2024-07-08 22:22:08 -07:00 |
|
tangxifan
|
fe06c2f2b1
|
[core] code format
|
2024-07-08 16:18:58 -07:00 |
|
tangxifan
|
db459b0e87
|
[core] add verbose outputs
|
2024-07-08 16:18:32 -07:00 |
|
tangxifan
|
e8f9deeeaf
|
[core] fixed a critical bug on computing pin index for subtile in clock taps
|
2024-07-08 16:12:20 -07:00 |
|
tangxifan
|
6dde383a7f
|
[core] debugging
|
2024-07-08 16:00:18 -07:00 |
|
tangxifan
|
8bca3d79be
|
[core] fixed a bug where tap points of clock network cannot reach perimeter cb
|
2024-07-08 15:17:24 -07:00 |
|
tangxifan
|
7bd60f5f7d
|
[core] support perimeter cb when identify pins of I/Os tiles
|
2024-07-08 12:39:54 -07:00 |
|
tangxifan
|
5c9c4d93c5
|
[core] typo
|
2024-07-08 10:46:47 -07:00 |
|
tangxifan
|
cdd477ad80
|
[core] remove restrictions on cb clock nodes
|
2024-07-08 10:14:39 -07:00 |
|
tangxifan
|
8449da0143
|
[core] typo
|
2024-07-07 23:36:13 -07:00 |
|
tangxifan
|
7996de3fe6
|
[core] now support perimeter cb in programmable clock network arch
|
2024-07-07 14:57:05 -07:00 |
|
tangxifan
|
703cbddc9e
|
[core] code format
|
2024-07-06 12:14:57 -07:00 |
|
tangxifan
|
6024e35f89
|
[core] fixed a bug
|
2024-07-05 18:50:14 -07:00 |
|
tangxifan
|
1f7fbfef64
|
[core] fixed a bug on inter-tile connections in top module
|
2024-07-05 18:19:22 -07:00 |
|
tangxifan
|
e95b264965
|
[core] debugging
|
2024-07-05 18:08:48 -07:00 |
|
tangxifan
|
cca9fb4756
|
[core] fixed a bug on bottom left tile organization
|
2024-07-05 17:55:19 -07:00 |
|
tangxifan
|
46d916f0a0
|
[core] fixed the bugs in fabric tile build-up
|
2024-07-05 16:59:08 -07:00 |
|
tangxifan
|
a41f437109
|
[core] now netlist look ok
|
2024-07-05 12:36:47 -07:00 |
|
tangxifan
|
283aa3a1c9
|
[core] debug
|
2024-07-05 12:21:17 -07:00 |
|
tangxifan
|
46e3b4b071
|
[core] debug
|
2024-07-05 11:50:41 -07:00 |
|
tangxifan
|
fdbc427f70
|
[core] debug
|
2024-07-05 11:17:05 -07:00 |
|
tangxifan
|
f6adca1545
|
[core] fixed a bug
|
2024-07-05 11:02:01 -07:00 |
|
tangxifan
|
1dc602a849
|
[core] syntax
|
2024-07-05 10:38:26 -07:00 |
|
tangxifan
|
266c2686d4
|
[core] adapt new gsb coordinate system
|
2024-07-05 10:32:33 -07:00 |
|
tangxifan
|
1f8c2436ef
|
[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
|
2024-07-04 20:46:38 -07:00 |
|
tangxifan
|
72ee39f178
|
[core] add new command line option 'constant_undriven_inputs'
|
2024-07-04 20:39:02 -07:00 |
|
tangxifan
|
4e21bbb3f1
|
[core] now support constant undriven local wires in verilog writer
|
2024-07-04 20:32:56 -07:00 |
|
tangxifan
|
1dd03d0fdd
|
[core] on a new feature to connect undriven pins to ground
|
2024-07-04 18:34:39 -07:00 |
|
tangxifan
|
6d798897fd
|
[lib] update vtr
|
2024-07-04 14:46:57 -07:00 |
|
tangxifan
|
f560fb8381
|
[core] more verbose
|
2024-07-04 14:27:17 -07:00 |
|
tangxifan
|
a8850d4f0f
|
[core] now verbose mode is applicable to more build top module cb instances
|
2024-07-04 14:22:30 -07:00 |
|
tangxifan
|
4b53e57c92
|
[core] fixed a bug
|
2024-07-04 13:33:04 -07:00 |