Commit Graph

8189 Commits

Author SHA1 Message Date
tangxifan c1f46c448a [core] fixed a critical bug where clock network entry is on a CHANY 2024-07-16 17:04:44 -07:00
tangxifan cbd10e1222 [core] fixed a bug where tile module's global port is not derived from dedicated clock network 2024-07-16 16:58:21 -07:00
tangxifan f607987386 [core] patch the out-of-range in clock rr nodes 2024-07-16 16:45:55 -07:00
tangxifan fc58daa239
Merge pull request #1748 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-07-10 16:58:40 -07:00
github-actions[bot] ab126d8cfc Updated Patch Count 2024-07-10 23:57:28 +00:00
tangxifan 1b9356e05c
Merge pull request #1747 from lnis-uofu/dependabot/submodules/yosys-b08688f
Bump yosys from `dac5bd1` to `b08688f`
2024-07-10 16:57:05 -07:00
tangxifan 37b302b335
Merge pull request #1746 from lnis-uofu/xt_clkntwk2
Support global net routing on regular inputs of programmable blocks
2024-07-10 16:56:47 -07:00
tangxifan 0c99fcf6f4 [doc] format 2024-07-10 15:07:57 -07:00
tangxifan c96f899c53 [core] code format 2024-07-10 15:07:26 -07:00
tangxifan a390aad0b8 [doc] add new syntax 2024-07-10 15:07:16 -07:00
tangxifan e614ca7380 [test] use new syntax 2024-07-10 15:03:27 -07:00
tangxifan a4538fb25b [core] now supports to_pin in building clock network for internal driver 2024-07-10 15:01:18 -07:00
tangxifan b2fc47a12a [core] reworked i/o for clock network files 2024-07-10 14:34:54 -07:00
tangxifan 079e6f2fca [core] add new syntax to support from_pin and to_pin for internal driver in clock network 2024-07-10 14:28:28 -07:00
tangxifan 215de8eb93 [core] code format 2024-07-10 14:17:22 -07:00
tangxifan f5ba43e392 [core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench 2024-07-10 14:16:24 -07:00
tangxifan 977283dd34 [core] typo 2024-07-10 14:12:49 -07:00
tangxifan af996e563e [test] add a new test to validate reset generated by internal driver through programmable clock network 2024-07-10 14:11:06 -07:00
tangxifan 213914e4ac [core] code format 2024-07-10 12:23:57 -07:00
tangxifan 48e159dd8d [core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches 2024-07-10 12:23:15 -07:00
tangxifan c6dd33a965 [core] fixed a bug when annotating global nets on OPIN 2024-07-10 11:59:25 -07:00
tangxifan b6ff69faac [test] reworking the testcase to validate clock network with internal drivers 2024-07-10 11:36:22 -07:00
tangxifan dbe8e63f53 [test] remove unused files 2024-07-10 10:15:47 -07:00
tangxifan 77304164f4 [test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W 2024-07-10 10:13:41 -07:00
tangxifan 191a3d1c5e [test] update W 2024-07-10 10:01:31 -07:00
tangxifan 81fe722d98 [test] adjust W 2024-07-09 23:49:01 -07:00
dependabot[bot] 66a77c8658
Bump yosys from `dac5bd1` to `b08688f`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `dac5bd1` to `b08688f`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](dac5bd1983...b08688f711)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
2024-07-10 06:25:00 +00:00
tangxifan 96bdcc8b35 [core] code format 2024-07-09 22:54:55 -07:00
tangxifan 63f2a07c86 [test] typo 2024-07-09 22:54:33 -07:00
tangxifan 27e29f949c [core] fixed a bug where the pin idx of global net on rr graph is not well annotated 2024-07-09 22:53:12 -07:00
tangxifan a16b3df063 [test] update arch to allow clock access on CLB inputs 2024-07-09 20:59:44 -07:00
tangxifan 0f78803759 [core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs 2024-07-09 20:47:15 -07:00
tangxifan 43dbeafd44 [test] typo 2024-07-09 20:27:28 -07:00
tangxifan 9ce4b57363 [test] typo 2024-07-09 20:25:39 -07:00
tangxifan e5d146a67a [test] add new tests to validate rst on lut and clk on lut features 2024-07-09 20:24:23 -07:00
tangxifan 89e6a0483f [test] add a new benchmark to validate rst and clk on LUTs 2024-07-09 18:45:33 -07:00
tangxifan 38bb5aa906 [test] add a new benchmark to validate clock on LUT 2024-07-09 18:42:39 -07:00
tangxifan a155ea4b41
Merge pull request #1743 from lnis-uofu/dependabot/submodules/yosys-dac5bd1
Bump yosys from `a739e21` to `dac5bd1`
2024-07-09 16:15:21 -07:00
tangxifan e3caff56ee
Merge pull request #1745 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-07-09 16:14:57 -07:00
github-actions[bot] f0e168c2b3 Updated Patch Count 2024-07-09 21:54:39 +00:00
tangxifan a2afdae0cc
Merge pull request #1741 from lnis-uofu/xt_clkntwk2
Support Connection Blocks on Perimeter Tiles
2024-07-09 14:54:16 -07:00
tangxifan f42884304a [doc] update clock network details 2024-07-09 11:40:41 -07:00
tangxifan 5efc9d0e00 [test] update golden outputs 2024-07-08 23:24:16 -07:00
tangxifan 092b8b038f [core] remove verbose out 2024-07-08 22:23:37 -07:00
tangxifan 04504e4d5d [core] code format 2024-07-08 22:22:59 -07:00
tangxifan 1cdb1c5995 [core] fixed a bug on calculating subtile pins 2024-07-08 22:22:08 -07:00
tangxifan 5cb104a5f6 [test] fixed a bug 2024-07-08 22:04:40 -07:00
tangxifan bf484dbc70 [doc] add perimeter cb examples on prog clk network 2024-07-08 21:25:12 -07:00
tangxifan 229adebe07 [doc] new option to write_fabric_verilog 2024-07-08 21:06:12 -07:00
tangxifan 41839bfd7a [test] typo 2024-07-08 20:21:40 -07:00